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    0213A Search Results

    0213A Result Highlights (1)

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    R7F7010213AFP Renesas Electronics Corporation High-end In-vehicle Microcomputers for Body Applications Visit Renesas Electronics Corporation
    SF Impression Pixel

    0213A Price and Stock

    Diodes Incorporated PI5USB30213AXEAEX

    USB3 SWITCH,X1-QFN2040-24
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    Panasonic Electronic Components AQH0213AZ

    SSR RELAY SPST-NO 300MA 0-600V
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    Panasonic Electronic Components AQH0213AX

    SSR RELAY SPST-NO 300MA 0-600V
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    Panasonic Electronic Components AQH0213A

    SSR RELAY SPST-NO 300MA 0-600V
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    Tripp Lite P006-002-13A

    CORD 16AWG NEMA5-15P - IEC320 2'
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    0213A Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Date Code Formats Altera

    Abstract: Cortex-m1 altera Date Code Formats intel date code format
    Text: Application Note 213 Cortex-M1 TCM initialization in the ARM Cortex-M1 FPGA Development Kit Altera Edition Document number: ARM DAI 0213A Issued: 2nd September, 2008 Copyright ARM Limited 2008 Copyright  2008 ARM Limited. All rights reserved. Non-Confidential Unrestricted Access


    Original
    PDF

    PT80

    Abstract: No abstract text available
    Text: ispLSI 81080V Features Functional Block Diagram • SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — 60,000 PLD Gates/1080 Macrocells — 192-360 I/O Pins Supporting 3.3V/2.5V I/O — 1440 Registers — High-Speed Global and Big Fast Megablock BFM


    Original
    1080V Gates/1080 20-Macrocell 492-Ball 0212/81080V 1080V-125LB272 272-Ball 1080V-125LB492 1080V-90LB272 PT80 PDF

    Untitled

    Abstract: No abstract text available
    Text: LeadFree a P ckage Options Available! ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay • IN-SYSTEM PROGRAMMABLE D0 C7 A1 ES


    Original
    2128/A OuLTN176 176-Pin 128A-80LQN160 160-Pin 128A-80LTN176 128A-80LTN176I PDF

    4032V

    Abstract: DS1017 LC4032V-10TN48I 4512c application LC4256V-75TN176C marking 17Z 4000B AEC-Q100 DS1020 22z2
    Text: ispMACH 4000V/B/C/Z Family 3.3V/2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs Coolest Power May 2009 C Features Data Sheet DS1020 TM • Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction Tj


    Original
    000V/B/C/Z DS1020 AEC-Q100 000V/Z 400MHz nonAEC-Q100 256-ftBGA 4A-07. 4000Z 000V/B/C 4032V DS1017 LC4032V-10TN48I 4512c application LC4256V-75TN176C marking 17Z 4000B DS1020 22z2 PDF

    B272

    Abstract: No abstract text available
    Text: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.


    Original
    Faste14 3192-100LM 240-Pin 3192-100LB272 272-Ball 3192-70LM 3192-70LB272 3192-70LMI B272 PDF

    2096VE

    Abstract: TQFP 128pin
    Text: ispLSI 2192VL Functional Block Diagram — — — — — 8000 PLD Gates 96 I/O Pins, Nine Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic


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    2192VL 2096VE 0139/2192VL 212A/2192VL 2192VL 2192VL-150LT128 128-Pin 2192VL-150LB144 144-Ball 2192VL-135LT128 2096VE TQFP 128pin PDF

    4032 k14

    Abstract: 4512c PX6A10 4256b L5591 a/4032 k14 am 4512C LC45 4064C m6 pt80
    Text: TM ispMACH 4000B/C Family 2.5V/1.8V In-System Programmable SuperFAST TM High Density PLDs December 2001 Data Sheet • Broad Device Offering Features • • • • ■ High Performance • fMAX = 350MHz maximum operating frequency • tPD = 2.5ns propagation delay


    Original
    4000B/C 350MHz 4000B) 4000C) LC4512C-5F256I LC4512C-75F256I LC4512C-10F256I TN1004) 4032 k14 4512c PX6A10 4256b L5591 a/4032 k14 am 4512C LC45 4064C m6 pt80 PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLSI 2032V/LV 3.3V High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 7.5 ns Propagation Delay A1 A2 D Q GLB A6 D Q D Q A5 D Q A3 A4


    Original
    032V/LV 0139Bisp/2000 44-Pin 032V-80LT44 2032LV-80LT44* 032V-60LJ44 2032LV-60LJ* PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLSI 2096V 3.3V High Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original
    128-Pin 0212/2096V 096V-80LT128 096V-80LQ128 096V-60LT128 096V-60LQ128 PDF

    2096VE

    Abstract: No abstract text available
    Text: ispLSI 2192VL 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram — — — — — 8000 PLD Gates 96 I/O Pins, Nine Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State


    Original
    2192VL 2096VE 0139/2192VL 2192VL 128-Pin 144-Ball 212A/2192VL 2192VL-150LT128 2096VE PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLSI 3256 High Density Programmable Logic Functional Block Diagram A1 OR Array A2 A3 B1 B2 B3 N C0 C1 C2 R D Q F1 Twin GLB F0 D Q E3 D Q E2 D Q E1 Global Routing Pool E0 C3 Output Routing Pool • 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE F2 D Q Array


    Original
    160-MQFP/3256 0212Aisp/3256 3256-70LM 160-Pin 3256-50LM 041A-08isp/3256 PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLSI 2064V 3.3V High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC • • Global Routing Pool GRP Input Bus A0 A1 A2 B5 Logic Array B3 B2 D Q GLB B4 D Q B1 D Q D Q Input Bus B6 B7 Output Routing Pool (ORP)


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    44-Pin 064V-80LJ84 84-Pin 064V-80LT100 100-Pin 064V-80LJ44 064V-80LT44 064V-60LJ84 PDF

    ispLSI 3256A

    Abstract: No abstract text available
    Text: ispLSI 3256A In-System Programmable High Density PLD Functional Block Diagram • HIGH-PERFORMANCE E CMOS TECHNOLOGY — fmax = 90 MHz Maximum Operating Frequency — tpd = 12 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable


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    0212/3256A 256A-90LM* 160-Pin 256A-90LQ 256A-70LM* 256A-70LQ 256A-50LM* ispLSI 3256A PDF

    2032VE

    Abstract: 2032VL
    Text: ispLSI 2032VL 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram Global Routing Pool GRP Input Bus Output Routing Pool (ORP) A0 A1 A2 D Q GLB Logic Array A7 A6 D Q D Q A5 D Q A3 Input Bus • SuperFAST HIGH DENSITY IN-SYSTEM


    Original
    2032VL 2032VE 2032VL-180LT48 2032VL-180LJ44 2032VL-180LB49 48-Pin 44-Pin 49-Ball 2032VL-135LT44 2032VL PDF

    2032VE

    Abstract: 2032ve110lb 49-BALL 2032VE110
    Text: ispLSI 2032VE 3.3V In-System Programmable High Density SuperFAST PLD Features Functional Block Diagram • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — — — — — A2 D Q GLB Logic Array A7 A6 D Q D Q A5 D Q Input Bus Input Bus A1 A3 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY


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    2032VE 0139Bisp/2000 Impl44 2032VE-180LB49 48-Pin 44-Pin 49-Ball 2032VE-135LT44 2032VE-135LT48 2032VE 2032ve110lb 2032VE110 PDF

    AA13

    Abstract: AA19 AC11 AC13 AD12
    Text: ispLSI 3320 In-System Programmable High Density PLD Functional Block Diagram J0 Output Routing Pool ORP G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR Array D Q E1 H2 H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool


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    212A/3320 3320-100LQ 208-Pin 3320-100LB320 320-Ball 3320-100LM* 3320-70LQ 3320-70LB320 AA13 AA19 AC11 AC13 AD12 PDF

    2064VE

    Abstract: 2064VL
    Text: ispLSI 2064VL 2.5V In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC • • • Input Bus Output Routing Pool ORP Input Bus A1 Logic Array B3 B2 D Q GLB B4 D Q B1 D Q


    Original
    2064VL Compatible64VL-135LT100 100-Pin 2064VL-135LB100 100-Ball 2064VL-135LJ44 44-Pin 2064VL-135LT44 2064VL-100LT100 2064VE 2064VL PDF

    2128E

    Abstract: No abstract text available
    Text: ispLSI 2128E In-System Programmable SuperFAST High Density PLD Functional Block Diagram • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 180 MHz Maximum Operating Frequency — tpd = 5.0 ns Propagation Delay — TTL Compatible Inputs and Outputs — 5V Programmable Logic Core


    Original
    2128E 176-TQFP/2128E 0212/2128E 2128E 2128E-180LT176 176-Pin 2128E-135LT176 PDF

    2096VE

    Abstract: 2192VE
    Text: ispLSI 2096VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State


    Original
    2096VE 2192VE Routing128 128-Pin 0212/2096VE 2096VE 2096VE-250LT128* 2096VE-200LT128 2192VE PDF

    2032E

    Abstract: No abstract text available
    Text: ispLSI 2032E In-System Programmable SuperFAST High Density PLD Functional Block Diagram Input Bus ® • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 225 MHz Maximum Operating Frequency — tpd = 3.5 ns Propagation Delay — TTL Compatible Inputs and Outputs


    Original
    2032E 48-Pin 2032E-200LJ44* 44-Pin 2032E-200LT44* 2032E-200LT48* 2032E PDF

    K614

    Abstract: 2128VE
    Text: ispLSI 2128VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram* • 3.3V LOW VOLTAGE 2128 ARCHITECTURE — Interfaces with Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 250MHz Maximum Operating Frequency


    Original
    2128VE 250MHz 2128VE-135LB208 208-Ball 2128VE-135LT100 100-Pin 2128VE-135LB100 100-Ball 2128VE-100LT176 176-Pin K614 2128VE PDF

    GAL 0042b

    Abstract: 1032E
    Text: ® ispLSI and pLSI 1032E High-Density Programmable Logic • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs


    Original
    1032E GAL 0042b 1032E PDF

    Untitled

    Abstract: No abstract text available
    Text: MOSFETS N CHANNEL POWER MOSFETS PACKAGE T 0213A A TO-66 •d m p u l s e DRAIN CURRENT AMPS VOLTS @ 0.5 ' d OHMS •d Continuous AMPS STFJ120 100 0.3 8.0 32 40 STFJ130 100 0.18 12.0 40 50 STFJ140 100 0.085 15.0 60 70 STFJ220 200 0.8 5.0 20 40 STFJ230 200


    OCR Scan
    STFJ120 STFJ140 STFJ220 STFJ230 STFJ240 STFJ320 STFJ330 STFJ340 STFJ420 STFJ430 PDF

    2T931A

    Abstract: KT853 2T926A KT838A 2T803A 2T809A 2T904A 2T808A 2T603 2T921A
    Text: g V ì^ fg : W SflÉptÉ! W ^ i$ î0 i0 û * W I I m ^7ù£-à.S& m p ,-À-& s i: r& mSÊmÈÈ •ï ' ^ f§ W % a s Ü lg S I W M 7 \ w Jkw s i 4; h# » ik « W 'ï illl ¡ P * te ili -X\ S I Iw 11 4-S U E S T am Ir ¿ « 1 1 1 » , ü i a Î3 & & C nPA BO H H M K


    OCR Scan
    MOKP51KOB, KTC631 TI2023 II2033 TT213 TI216 fI217 II302 XI306 n306A 2T931A KT853 2T926A KT838A 2T803A 2T809A 2T904A 2T808A 2T603 2T921A PDF