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    1/3 CONVOLUTIONAL ENCODER Search Results

    1/3 CONVOLUTIONAL ENCODER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    74HC4051FT Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, TSSOP16B, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    TC4511BP Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, BCD-to-7-Segment Decoder, DIP16 Visit Toshiba Electronic Devices & Storage Corporation
    74HC4051D Toshiba Electronic Devices & Storage Corporation CMOS Logic IC, SP8T(1:8)/Analog Multiplexer, SOIC16, -40 to 125 degC Visit Toshiba Electronic Devices & Storage Corporation
    54LS147J/B Rochester Electronics LLC 54LS147 - Priority Encoders Visit Rochester Electronics LLC Buy
    AM7992BPC Rochester Electronics LLC AM7992B - Manchester Encoder/Decoder, PDIP24 Visit Rochester Electronics LLC Buy

    1/3 CONVOLUTIONAL ENCODER Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    2040b

    Abstract: scrambler satellite v.35 STEL-2040B scrambler v.35 algorithm G3N1 STEL-5268 STEL-2040A
    Text: Network Communications Group - Cable Network Operation STEL-2040B Data Sheet STEL-2040B Convolutional Encoder Viterbi Decoder 1 STEL-2040B FEATURES n Constraint Length 7 n Coding Gain of 5.2 dB @ 10-5 BER, Rate 1/2 n Rates 1/3 , 1/2 , 2/3* and 3/4* (*Punctured)


    Original     		STEL-2040B 68-pin CHP3-105 2040b scrambler satellite v.35 STEL-2040B scrambler v.35 algorithm G3N1 STEL-5268 STEL-2040A PDF

    scrambler satellite v.35

    Abstract: scrambler v.35 algorithm branch metric g1d1 sm2c convolutional G3N1 IESS-308 sCRAMBLER
    Text: STEL-2050A Data Sheet STEL-2050A Convolutional Encoder Viterbi Decoder R FEATURES • Constraint Length 7 ■ Coding Gain of 5.2 dB @ 10-5 BER, Rate 1/2 ■ Rates 1/3 , 1/2 , 2/3* and 3/4* (*Punctured) ■ Industry Standard Polynomials ■ Built in BER Monitor


    Original     		STEL-2050A 28-pin scrambler satellite v.35 scrambler v.35 algorithm branch metric g1d1 sm2c convolutional G3N1 IESS-308 sCRAMBLER PDF

    g3d0

    Abstract: PLCC 68 intel package dimensions "7 Bit Shift Register" data scrambler reference signal every symbols STEL-5268 2040a convolutional scrambler satellite v.35
    Text: STEL-2040A Data Sheet STEL-2040A Convolutional Encoder Viterbi Decoder R FEATURES • Constraint Length 7 ■ Coding Gain of 5.2 dB @ 10-5 BER, Rate 1/2 ■ Rates 1/3 , 1/2 , 2/3* and 3/4* (*Punctured) ■ Industry Standard Polynomials ■ Built in BER Monitor


    Original     		STEL-2040A 68-pin 70301A g3d0 PLCC 68 intel package dimensions "7 Bit Shift Register" data scrambler reference signal every symbols STEL-5268 2040a convolutional scrambler satellite v.35 PDF

    STEL-5269 512

    Abstract: AN 5269 qpsk transmitter STEL-5269 74HC74 decoder STEL-5268 convolutional convolutional encoder interleaving bpsk modulator STEL-5269+512
    Text: STEL-5269+512 Data Sheet STEL-5269+512 Convolutional Encoder Viterbi Decoder R FEATURES • CONSTRAINT LENGTH 7 ■ CODING RATES 1/2 AND 1/3 ■ THREE BIT SOFT-DECISION INPUTS IN ■ CODING GAIN OF 6.0 dB AT 10–5 BER, RATE 1/3 ■ INDUSTRY STANDARD POLYNOMIALS


    Original     		STEL-5269 STEL-5269 512 AN 5269 qpsk transmitter 74HC74 decoder STEL-5268 convolutional convolutional encoder interleaving bpsk modulator STEL-5269+512 PDF

    m6010

    Abstract: No abstract text available
    Text: A BROADCOM BCM6010 B C M 6 BCM6010 PK ® ADSL/VDSL F E A T U R E S • Integrated QAMLink Transmitter • Packet formatting, scrambling, and interleaving • R eed-Solom on FEC encoder • 0 - 1 3 MBaud variable rate 4-256 QAM modulator • Programmable depth convolutional interleaver


    OCR Scan     		BCM6010 10-bit BCM6012PB. m6010 PDF

    GP017

    Abstract: No abstract text available
    Text: Block Convolutional Encoder User’s Guide June 2010 IPUG31_03.5 Table of Contents Chapter 1. Introduction . 4 Quick Facts . 4


    Original     		IPUG31 LFSC/M3GA25E-7F900C D-2009 12L-1 GP017 PDF

    Convolutional Encoder

    Abstract: ispLEVER project Navigator Convolutional encoder verilog coding Convolutional Puncturing Pattern digital clock project Convolutional decoder polynomial Viterbi Decoder ispLEVER project Navigator route place
    Text: Convolutional Encoder User’s Guide April 2003 ipug03_02 Lattice Semiconductor Convolutional Encoder User’s Guide Introduction Lattice’s Convolutional Encoder core is a parameterizable core for convolutional encoding of a continuous input data stream. The core allows variable code rates, constraint lengths and generator polynomials. The core also supports puncturing. Puncturing enables a large range of transmission rates and reduces the bandwidth requirement


    Original     		ipug03 1-800-LATTICE Convolutional Encoder ispLEVER project Navigator Convolutional encoder verilog coding Convolutional Puncturing Pattern digital clock project Convolutional decoder polynomial Viterbi Decoder ispLEVER project Navigator route place PDF

    Untitled

    Abstract: No abstract text available
    Text: ispLever CORE TM Convolutional Encoder User’s Guide October 2005 ipug03_03.0a October 10, 2005 9:48 a.m. Lattice Semiconductor Convolutional Encoder User’s Guide Introduction Lattice’s Convolutional Encoder core is a parameterizable core for convolutional encoding of a continuous input


    Original     		ipug03 thX1200B, FE680, PDF

    Convolutional Encoder

    Abstract: 171OCT Convolutional convolutional encoder interleaving BYP 303 ENCODER GMBH A112 AN2835 MRC6011 x8 encoder
    Text: Freescale Semiconductor Application Note AN2835 Rev. 0, 9/2004 Building a Convolutional Encoder Using RCF Technology by Wim Rouwet Convolutional encoding is a forward error correcting FEC process associated with a Viterbi decoder on the receive side. Adding redundancy to the input data before it is sent to the


    Original     		AN2835 Convolutional Encoder 171OCT Convolutional convolutional encoder interleaving BYP 303 ENCODER GMBH A112 AN2835 MRC6011 x8 encoder PDF

    Convolutional Encoder

    Abstract: CORE i3 block diagram CORE i3 timing diagram Convolutional core i5 Convolutional Puncturing Pattern polynomials LFX1200B OR4E02 V711
    Text: Convolutional Encoder March 2003 IP Data Sheet Features General Description • Parameterizable continuous convolutional encoder The top-level representation of the convolutional encoder is shown in Figure 1. For detailed signal descriptions, see Table 1.


    Original     		PDF

    Convolutional Encoder

    Abstract: xilinx vhdl codes convolutional encoder source code X9064
    Text: ac_cselt_conv_enc.fm Page 1 Wednesday, March 14, 2001 12:30 PM CONV_ENC Convolutional Encoder December 07, 2000 Product Specification AllianceCORE Facts Tilab Via G. Reiss Romoli, 274 10148 Torino, Italy Phone: +39 011 228 5659 Fax: +39 011 228 7140 E-mail: [email protected]


    Original     		PDF

    Convolutional Encoder

    Abstract: Convolutional CORE i3 block diagram Convolutional Puncturing Pattern LFEC20E-5F672C GP113
    Text: Block Convolutional Encoder September 2004 IP Data Sheet Features General Description • Compatible with the Following Standards: IEEE 802.16, IEEE 802.16a, IEEE 802.11a, 3GPP, 3GPP2 and DVB-S Lattice’s Block Convolutional Encoder IP core is a parameterizable core for convolutional encoding of a


    Original     		PDF

    Convolutional Encoder

    Abstract: iess-309 standard IESS-309 IESS309 Convolutional CS3411 encoder verilog coding Implementation of convolutional encoder IESS-308 code CS3311AA
    Text: CS3311 TM Convolutional Encoder Virtual Components for the Converging World The CS3311 Convolutional Encoder is a high performance implementation suitable for a range of Forward Error Correction applications. This highly integrated application specific core can be used in conjunction with other


    Original     		CS3311 CS3311 CS341uo-ku DS3311 Convolutional Encoder iess-309 standard IESS-309 IESS309 Convolutional CS3411 encoder verilog coding Implementation of convolutional encoder IESS-308 code CS3311AA PDF

    Convolutional Encoder

    Abstract: vhdl code for spartan 6 Convolutional xilinx vhdl codes encoder simulator FSM VHDL encoder source code vhdl coding xilinx vhdl code
    Text: CONV_ENC Convolutional Encoder January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: [email protected] URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and


    Original     		I-10148 Convolutional Encoder vhdl code for spartan 6 Convolutional xilinx vhdl codes encoder simulator FSM VHDL encoder source code vhdl coding xilinx vhdl code PDF

    ETS-300-421

    Abstract: Convolutional convolutional interleaver 16QAM Reed-Solomon Decoder for DVB application smc96 6 PTCM 8PSK television internal parts block diagram SMC-960A
    Text: SMC-960A Integrated Digital Encoder/Pulse-Shaper General Description Featur es The SMC-960A is an integrated PSK/QAM encoder/pulse-shaper with forward error correction FEC that is fully compliant with the European Digital Video Broadcasting Standard, ETS-300-421. It supports variable symbol rates and all 5 convolutional code


    Original     		SMC-960A SMC-960A ETS-300-421. 16QAM 014-A0011 ETS-300-421 Convolutional convolutional interleaver 16QAM Reed-Solomon Decoder for DVB application smc96 6 PTCM 8PSK television internal parts block diagram PDF

    viterbi convolution

    Abstract: 16-PSK 16psk Convolutional Encoder Convolutional DS3310 CS3310 CS3310AA CS3310TK 16psk block diagram
    Text: CS3310 TM Programmable Convolution Encoder Virtual Components for the Converging World The CS3310 Programmable Convolutional Encoder is a high performance implementation suitable for a range of Forward Error Correction applications. This highly integrated Application Specific Virtual Components ASVC


    Original     		CS3310 CS3310 DS3310 viterbi convolution 16-PSK 16psk Convolutional Encoder Convolutional CS3310AA CS3310TK 16psk block diagram PDF

    16psk block diagram

    Abstract: Implementation of convolutional encoder differential encoder for psk viterbi convolution 16PSK Convolutional CS3310 convolution encoder uPI Semiconductor CS3310TK
    Text: CS3310 TM Programmable Convolution Encoder Virtual Components for the Converging World The CS3310 Programmable Convolutional Encoder is a high performance implementation suitable for a range of Forward Error Correction applications. This highly integrated Application Specific Virtual Components ASVC


    Original     		CS3310 CS3310 silicon256 DS3310-a 16psk block diagram Implementation of convolutional encoder differential encoder for psk viterbi convolution 16PSK Convolutional convolution encoder uPI Semiconductor CS3310TK PDF

    Convolutional Encoder

    Abstract: CS3530 Convolutional Block Interleaver time interleaver "Single-Port RAM" turbo encoder circuit
    Text: CS3530 TM Turbo Encoder Virtual Components for the Converging World The CS3530 Turbo Encoder is designed to provide efficient and high performance solutions for a broad range of applications requiring reliable communications in bandwidth scarce environments such as satellite and mobile


    Original     		CS3530 CS3530 CDMA2000 DS3530 Convolutional Encoder Convolutional Block Interleaver time interleaver "Single-Port RAM" turbo encoder circuit PDF

    STEL-2030C

    Abstract: scrambler v.35 algorithm 74AC298 IESS-308 sCRAMBLER 74AC74 84-PIN STEL2030B qpsk encoder 16 bit scrambler satellite v.35 viterbi algorithm
    Text: STEL-2030C Data Sheet STEL-2030C 17 Mbps Convolutional Encoder Viterbi Decoder R FEATURES FUNCTIONAL DESCRIPTION n 17 Mbps MAX. OPERATING DATA RATE n CONSTRAINT LENGTH K = 7 G1 = 1718, G2 = 1338 n MULTIPLE DEVICES CAN BE MULTIPLEXED TO GIVE HIGHER DATA RATES


    Original     		STEL-2030C STEL-2030C scrambler v.35 algorithm 74AC298 IESS-308 sCRAMBLER 74AC74 84-PIN STEL2030B qpsk encoder 16 bit scrambler satellite v.35 viterbi algorithm PDF

    vhdl code for interleaver

    Abstract: vhdl code for block interleaver design for block interleaver deinterleaver RE35 umts turbo encoder vhdl code download REED SOLOMON convolutional interleaver Convolutional interleaver by vhdl interleaver time
    Text: Symbol Interleaver/Deinterleaver MegaCore Function User Guide Version 1.2 August 2000 Symbol Interleaver/Deinterleaver MegaCore Function User Guide, August 2000 A-UG-INTERLEAVER-01.2 ACCESS, Altera, AMPP, APEX, APEX 20K, Atlas, FLEX, FLEX 10K, FLEX 10KA, FLEX 10KE, FLEX 6000, FLEX 6000A, MAX, MAX+PLUS,


    Original     		-UG-INTERLEAVER-01 vhdl code for interleaver vhdl code for block interleaver design for block interleaver deinterleaver RE35 umts turbo encoder vhdl code download REED SOLOMON convolutional interleaver Convolutional interleaver by vhdl interleaver time PDF

    scrambler v.35 algorithm

    Abstract: scrambler satellite v.35
    Text: STEL-2070A Data Sheet STEL-2070A Dual Constraint Length K=7,9 Convolutional Encoder Viterbi Decoder R Powered by ICminer.com Electronic-Library Service CopyRight 2003 FEATURES • Dual Constraint Length: 7 or 9 ■ Coding Gain: 5.2 dB (@ 10-5 BER, K = 7)


    Original     		STEL-2070A scrambler v.35 algorithm scrambler satellite v.35 PDF

    vhdl code for interleaver

    Abstract: vhdl code for block interleaver design for block interleaver deinterleaver interleaver by vhdl interleaver Convolutional ahdl code for deinterleaver "Single-Port RAM" Convolutional Encoder Interleaver-De-interleaver
    Text: Symbol Interleaver/Deinterleaver MegaCore Function Solution Brief 42 September 2000, ver. 2.0 Target Applications: Features Digital Communications • ■ ■ ■ Family: APEXTM 20K & FLEX 10K Ordering Code: PLSM-INLV General Description Vendor: ® 101 Innovation Drive


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    scrambler v.35 algorithm

    Abstract: scrambler satellite v.35 scrambler v.35 diagram CNT-240 STEL-2070A bpsk modulator low frequency bpsk modulator ic CNT2423-0 CNT160 convolutional
    Text: STEL-2070A Data Sheet STEL-2070A Dual Constraint Length K=7,9 Convolutional Encoder Viterbi Decoder R FEATURES • Dual Constraint Length: 7 or 9 ■ Coding Gain: 5.2 dB (@ 10-5 BER, K = 7) ■ Rate 1/2 6.0 dB (@ 10-5 BER, K = 9) ■ Three Bit Soft Decision Inputs in Signed


    Original     		STEL-2070A scrambler v.35 algorithm scrambler satellite v.35 scrambler v.35 diagram CNT-240 STEL-2070A bpsk modulator low frequency bpsk modulator ic CNT2423-0 CNT160 convolutional PDF

    interleaver

    Abstract: "Single-Port RAM" design for convolutional interleaver deinterleaver Convolutional design for block interleaver deinterleaver block convolutional interleaving
    Text: Interleaver/Deinterleaver MegaCore Function Solution Brief 42 June 1999, ver. 1 Target Applications: Digital communications systems, digital audio and video broadcast systems, and data storage and retrieval systems Family: APEXTM 20K & FLEX 10K Features


    Original     		PDF