SOP 8 200MIL
Abstract: serial flash 256Mb fast erase spi TM 1628 IC SOP Micron 512MB NOR FLASH HN29V1G91T-30 HN58C1001FPI-15 M5M51008DFP-70HI 256mb EEPROM Memory CSP-48 TSOP 28 SPI memory Package flash
Text: Renesas Memory General Catalog 2003.11 Renesas Memory General Catalog Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
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D-85622
REJ01C0001-0100Z
SOP 8 200MIL
serial flash 256Mb fast erase spi
TM 1628 IC SOP
Micron 512MB NOR FLASH
HN29V1G91T-30
HN58C1001FPI-15
M5M51008DFP-70HI
256mb EEPROM Memory
CSP-48
TSOP 28 SPI memory Package flash
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PDF
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CY7C1355C
Abstract: No abstract text available
Text: CY7C1355C, CY7C1357C 9-Mbit 256 K x 36 / 512 K × 18 Flow-Through SRAM with NoBL Architecture 9-Mbit (256 K × 36 / 512 K × 18) Flow-through SRAM with NoBL™ Architecture Features Functional Description • No Bus Latency™ (NoBL™) architecture eliminates dead
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CY7C1355C,
CY7C1357C
CY7C1355C/CY7C1357C
CY7C1355C
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PDF
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CY7C1382DV33-200BZI
Abstract: No abstract text available
Text: CY7C1380DV33 CY7C1382DV33 18-Mbit 512 K x 36/1 M × 18 Pipelined SRAM 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM Features Functional Description • Supports bus operation up to 200 MHz ■ Available speed grades is 200 MHz ■ Registered inputs and outputs for pipelined operation
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CY7C1380DV33
CY7C1382DV33
18-Mbit
CY7C1380DV33/CY7C1382DV33
CY7C1382DV33-200BZI
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PDF
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Untitled
Abstract: No abstract text available
Text: CY7C1352G 4-Mbit 256 K x 18 Pipelined SRAM with NoBL Architecture 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need
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CY7C1352G
CY7C1352G
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Untitled
Abstract: No abstract text available
Text: CY7C1347G 4-Mbit 128 K x 36 Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features Functional Description • Fully registered inputs and outputs for pipelined operation ■ 128 K × 36 common I/O architecture ■ 3.3 V core power supply (VDD)
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CY7C1347G
CY7C1347G
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IS61LPS102418A
Abstract: IS61LPS25672A IS61LPS51236A IS61VPS102418A IS61VPS25672A IS61VPS51236A IS61LPS51236A-200TQLI 1024Kx18
Text: IS61VPS25672A IS61LPS25672A IS61VPS51236A IS61LPS51236A IS61VPS102418A IS61LPS102418A ISSI 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write
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IS61VPS25672A
IS61LPS25672A
IS61VPS51236A
IS61LPS51236A
IS61VPS102418A
IS61LPS102418A
1024K
JEDE30
PK13197LQ
5M-1982.
IS61LPS102418A
IS61LPS25672A
IS61LPS51236A
IS61LPS51236A-200TQLI
1024Kx18
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N18N1825F1B
Abstract: N18N1833F1B N18N3625F1B N18N3633F1B
Text: N18N1825F1B N18N1833F1B N18N3625F1B N18N3633F1B NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877 www.nanoamp.com 18Mb High Speed Synchronous Flow-Thru SRAMs with Fast bus Turnaround FTRAMTM Architecture Features
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N18N1825F1B
N18N1833F1B
N18N3625F1B
N18N3633F1B
133MHz
N18N1825F1BQ-
N18N3625F1BQ-
N18N1833F1BF-
165-FPBGA
N18N3633F1BF-
N18N1833F1B
N18N3633F1B
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IS61LPD51218A
Abstract: IS61LPD25636A IS61VPD25636A IS61VPD51218A
Text: ISSI IS61VPD25636A IS61LPD25636A IS61VPD51218A IS61LPD51218A 256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and
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IS61VPD25636A
IS61LPD25636A
IS61VPD51218A
IS61LPD51218A
100-Pin
119-pin
165-pin
PK13197LQ
5M-1982.
IS61LPD51218A
IS61LPD25636A
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IS61LPS25632A
Abstract: IS61LPS25636A IS61LPS51218A IS61VPS25636A IS61VPS51218A
Text: IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write
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IS61LPS51218A,
IS61LPS25636A,
IS61LPS25632A,
IS64LPS25636A,
IS61VPS51218A,
IS61VPS25636A
PK13197LQ
5M-1982.
IS61LPS25632A
IS61LPS25636A
IS61LPS51218A
IS61VPS25636A
IS61VPS51218A
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IS64LF12832A-7
Abstract: is64lf12832a LF12836A E0108 IS61LF12836A-6.5B3
Text: IS61 64 LF12832A IS64VF12832A IS61(64)LF12836A IS61(64)VF12836A IS61(64)LF25618A IS61(64)VF25618A 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write
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LF12832A
IS64VF12832A
LF12836A
VF12836A
LF25618A
VF25618A
100-Pin
119-pin
165-pin
LF12832A,
IS64LF12832A-7
is64lf12832a
E0108
IS61LF12836A-6.5B3
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Untitled
Abstract: No abstract text available
Text: CY7C1361A CY7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0ns Fast clock speed: 150, 133, 117, and 100MHz Fast OE access times: 3.5 ns and 4.0 ns
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CY7C1361A
CY7C1363A
36/512K
100MHz
CY7C1361A/CY7C1363A
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Untitled
Abstract: No abstract text available
Text: IS61NLF12836A/IS61NVF12836A IS61NLF25618A/IS61NVF25618A 128K x 36 and 256K x 18 4Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM MAY 2007 FEATURES DESCRIPTION • 100 percent bus utilization The 4 Meg 'NLF/NVF' product family feature high-speed, low-power synchronous static RAMs designed to provide
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IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
100-pin
119-ball
165ball
5M-1982.
PK13197LQ
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Untitled
Abstract: No abstract text available
Text: IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A, IS61VPS51218A, IS61VPS25636A 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write
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Original
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IS61LPS51218A,
IS61LPS25636A,
IS61LPS25632A,
IS64LPS25636A,
IS61VPS51218A,
IS61VPS25636A
100-Pin
119-bC
5M-1982.
PK13197LQ
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CY7C1386C
Abstract: CY7C1387C
Text: CY7C1386C CY7C1387C 18-Mb 512K x 36/1M x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200 and 167 MHz • Registered inputs and outputs for pipelined operation
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CY7C1386C
CY7C1387C
18-Mb
36/1M
250-MHz
CY7C1386C/CY7C1387C
CY7C1386C
CY7C1387C
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Untitled
Abstract: No abstract text available
Text: IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM ISSI PRELIMINARY INFORMATION JANUARY 2005 FEATURES DESCRIPTION • 100 percent bus utilization The 9 Meg 'NLP/NVP' product family feature high-speed,
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IS61NLP25636A/IS61NVP25636A
IS61NLP51218A/IS61NVP51218A
PK13197LQ
5M-1982.
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CY7C1325G
Abstract: CY7C1325G-133AXC CY7C1325G-133AXI CY7C1325G-133BGC CY7C1325G-133BGI CY7C1325G-133BGXC CY7C1325G-133BGXI
Text: CY7C1325G PRELIMINARY 4-Mbit 256K x 18 Flow-Through Sync SRAM Functional Description[1] Features • 256K X 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version)
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CY7C1325G
133-MHz
117-MHz
100-MHz
100-pin
119-ball
CY7C1325G
CY7C1325G-133AXC
CY7C1325G-133AXI
CY7C1325G-133BGC
CY7C1325G-133BGI
CY7C1325G-133BGXC
CY7C1325G-133BGXI
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Untitled
Abstract: No abstract text available
Text: IS61NLF12836A/IS61NVF12836A IS61NLF25618A/IS61NVF25618A ISSI PRELIMINARY INFORMATION SEPTEMBER 2005 128K x 36 and 256K x 18 4Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM FEATURES DESCRIPTION • 100 percent bus utilization The 4 Meg 'NLF/NVF' product family feature high-speed,
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IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
PK13197LQ
5M-1982.
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CY7C1327B
Abstract: No abstract text available
Text: 327 CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM Features The CY7C1327B I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V. • Supports 100-MHz bus for Pentium and PowerPC operations with zero wait states
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CY7C1327B
CY7C1327B
100-MHz
166-MHz
166-Mpress
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CY7C1381B-100AI
Abstract: 381B CY7C1381B CY7C1381B-117AC CY7C1383B
Text: 381B CY7C1381B CY7C1383B 512 x 36/1M × 18 Flow-Thru SRAM Features • • • • • • • • • • • Fast access times: 7.5, 8.5, 10.0 ns Fast clock speed: 117, 100, 83 MHz Provide high-performance 3-1-1-1 access rate Optimal for depth expansion
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CY7C1381B
CY7C1383B
36/1M
CY7C1381B/CY7C1383B
x36/1M
CY7C1381B-100AI
381B
CY7C1381B
CY7C1381B-117AC
CY7C1383B
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80486 microprocessor block diagram and pin diagram
Abstract: CY7C1338B
Text: 338B CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times — 7.5 ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence
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CY7C1338B
117-MHz
100-pin
CY7C1338B
80486 microprocessor block diagram and pin diagram
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CY7C1354C
Abstract: CY7C1356C
Text: CY7C1354C CY7C1356C 9-Mbit 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Functional Description[1] Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200, and 166 MHz
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CY7C1354C
CY7C1356C
36/512K
250-MHz
CY7C1354C
CY7C1356C
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PDF
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CY7C1327G
Abstract: CY7C1327G-250AXC CY7C1327G-250AXI CY7C1327G-250BGC CY7C1327G-250BGI CY7C1327G-250BGXC CY7C1327G-250BGXI
Text: CY7C1327G PRELIMINARY 4-Mbit 256K x 18 Pipelined Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • 256K x18 common I/O architecture • 3.3V core power supply • 3.3V / 2.5V I/O operation • Fast clock-to-output times
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CY7C1327G
250-MHz
225-MHz
200-MHz
CY7C1327G
CY7C1327G-250AXC
CY7C1327G-250AXI
CY7C1327G-250BGC
CY7C1327G-250BGI
CY7C1327G-250BGXC
CY7C1327G-250BGXI
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GVT71256ZC36B-7.5
Abstract: CY7C1356A-100AC CY7C1356A GVT71512ZC18
Text: PRELIMINARY CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256Kx36/512Kx18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast clock speed: 200, 166, 133, and 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns
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CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
256Kx36/512Kx18
GVT71256ZC36B-7.5
CY7C1356A-100AC
CY7C1356A
GVT71512ZC18
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CY7C1361V25
Abstract: CY7C1363V25
Text: C Y 7 C 1 3 6 1 V 25 C Y 7 C 1 3 6 3 V 25 PRELIMINARY ~= C Y P H hbb = 256K x 36 / 512K x 18 Flowthrough SRAM Functional Description Features • Supports 113-MHz bus operations The CY7C1361V25 and CY7C1363V25 are 2.5v, 256K x 36 and 512K x 18 synchronous-flowthrough SRAM designed to
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OCR Scan
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CY7C1361V25
CY7C1363V25
113-MHz
117-MHz
100-MHz
80-MHz
100-pin
CY7C1361V25
CY7C1363V25
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