teradyne z1890
Abstract: Sis 968 ispMACH 4000 development circuit gal amd 22v10 22v10 pal gal programming 22v10 Pal programming 22v10 272-BGA GAL programming PALCE* programming
Text: L A T T I C E S E M I C O N D U C T Programmable Logic Devices O R “A vision of the ultimate system — Lattice provides the tools and analog, digital, and everything in support necessary to utilize each between, instantly re-programmable.” of these building blocks. The
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I0107A
teradyne z1890
Sis 968
ispMACH 4000 development circuit
gal amd 22v10
22v10 pal
gal programming 22v10
Pal programming 22v10
272-BGA
GAL programming
PALCE* programming
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"XOR Gate"
Abstract: 5000VA 5384VE
Text: ispLSI 5000V Family Architectural Description December 2001 Introduction The ispLSI 5000V Family of In-System Programmable SuperWIDE High Density Logic Devices offers two generations: ispLSI 5000VE and 5000VA. They are based on Generic Logic Blocks GLBs of 32 registered macrocells
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5000VE
5000VA.
5000VE/VA
"XOR Gate"
5000VA
5384VE
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TDK ZCB2206-11
Abstract: TDK noise FILTER zcb2206 ZCB2206-11 E53-S W267 E53-q voltage unit E53-Q E53-C E53-Q3 E53-V35
Text: Process Controller with DeviceNet E5EK-DRT Process Controller Conforming to DeviceNet Conforms to the DeviceNet and connects to a programmable logic controller without any programming High performance range of 0.1% FS Pt input: -100.0C to 100.0C
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H099-E3-1.
1-800-55-OMRON
GCTC12
TDK ZCB2206-11
TDK noise FILTER zcb2206
ZCB2206-11
E53-S
W267
E53-q voltage unit
E53-Q
E53-C
E53-Q3
E53-V35
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therm-o-disc 59T wiring diagram
Abstract: therm-o-disc 59T wiring diagram 66TM 125 va pt dty 59T4190 therm-o-disc 100 59T4200 CS8323 ignition transformer
Text: 59T, 66T Series Electric Water Heater Controls Snap-Action Bimetal Discs in Both Controls The 59T and 66T series controls are designed to meet the high electrical capacity requirements of electric water heaters. Both use a temperature sensitive bimetal disc to deliver snap action to the
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therm-o-disc 59T wiring diagram
Abstract: No abstract text available
Text: 59T, 66T Series Electric Water Heater Controls Snap-Action Bimetal Discs in Both Controls The 59T and 66T series controls are designed to meet the high electrical capacity requirements of electric water heaters. Both use a temperature sensitive bimetal disc to deliver snap-action to the
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683XX
Abstract: 68HC11 68HC16 A15F PSD411A1 PSD411A2 psd4xx flip flop T
Text: Programmable Peripheral PSD413F Family Avance Information Introduction Field-Programmable Microcontroller Peripherals with Flash Memory The PSD413F family of products is the first PSD family to bring the benefits of in-system programming to the embedded system designer. This new family is implemented with WSI’s
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PSD413F
PSD413
PSD411A1
PSD411A2
683XX
68HC11
68HC16
A15F
psd4xx
flip flop T
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Avance Logic
Abstract: Z80 CPU APD Arrays Avance Logic A15F PIN DIAGRAM OF 80186 683XX 68HC11 68HC16 PSD411A1 PSD411A2
Text: Programmable Peripheral PSD413F Family Avance Information Introduction Field-Programmable Microcontroller Peripherals with Flash Memory The PSD413F family of products is the first PSD family to bring the benefits of in-system programming to the embedded system designer. This new family is implemented with WSI’s
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PSD413F
PSD413
PSD411A1
PSD411A2
Avance Logic
Z80 CPU
APD Arrays
Avance Logic A15F
PIN DIAGRAM OF 80186
683XX
68HC11
68HC16
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FZ 44 NS
Abstract: 1N3064 3CP51
Text: MIl-N-3Mie/442A 9 AtwfSt 1983 sirPF ffSEirnre-MIL-M-38510/442 USAF 8 Ma rc h 1979 IQUAL 1h 1 (JA I IHN I IRE QU IREMENTS I I REMOVED I M I LI TA RY SPECIFICATION MICROCIR CU IT S, DIGITAL, SCHOTTKY, TTL, D-TYPE REGISTER, W I TH TH REE-STATE OUTPUT, MO NO L I T H I C SILICON
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1UA11UNI
MIl-N-3Mie/442A
MIL-M-38510/442
-M-38510/442A
706-040/S2B1
FZ 44 NS
1N3064
3CP51
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IR detector odti make
Abstract: Theta-JC QFP die down 7181 47 CHB 4U1 by 808 dfx PBS-2 CONNECTOR data sheet IC 7404 pml 017 38A IR receiver data sheet 51ED2
Text: PM P re lim in a r y In fo rm a tio n D a ta S h e e t • I PM C-960840 IS S U E 3 ^ 1 PM C-Sierra, Inc. # I PM 4388 TOCTL OCTAL T1 FRAMER FEATURES • Integrates eight T1 fra m e rs in a sin g le d evice fo r term inating duplex DS-1 signals. • S upports S F a nd E S F fo rm a t DS-1 signals.
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PM4388
PMC-960840
14x20x2
000751b
IR detector odti make
Theta-JC QFP die down
7181
47 CHB 4U1
by 808 dfx
PBS-2 CONNECTOR
data sheet IC 7404
pml 017
38A IR receiver data sheet
51ED2
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Untitled
Abstract: No abstract text available
Text: IDT54/74FCT543 IDT54/74FCT543A IDT54/74FCT543C FAST CMOS OCTAL LATCHED TRANSCEIVER Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • IDT54/74FCT543 equivalent to FAST speed The IDT54/74FCT543/A/C is a non-inverting octal trans ceiver built using an advanced dual metal CMOS technology.
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IDT54/74FCT543
IDT54/74FCT543A
IDT54/74FCT543C
IDT54/74FCT543
IDT54/74FCT543/A/C
IDT54/74FCT543/A/C
MIL-STD-883,
DG15fl25
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Untitled
Abstract: No abstract text available
Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors :JÖi'Np Jdt) PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Common I/O TAG Bits - 2 Separate I/O Status Bits (VLD and DTY) • Optimized for 256KB cache and 4GB cacheable space
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8Kx16-BIT)
IDT71V218
256KB
48-pin
8Kx16
200mV
71V218
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2574A
Abstract: No abstract text available
Text: CY54/74FCT2374T CY54/74FCT2574T 8-BIT REGISTERS ^ R T cypress FEATURES • Function and pin compatible with FCT & F logic ■ Power-off disable feature ■ 25£2 output series resistors to reduce transmission line reflection noise ■ Matched Rise and Fall times
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CY54/74FCT2374T
CY54/74FCT2574T
2374T/2574T
2374AT/2574AT
2374CT/2574CT
MIL-STD-883,
2574A
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Untitled
Abstract: No abstract text available
Text: P54/74FCT399T/AT/CT FAST QUAD DUAL-PORT REGISTER FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic ESD protection exceeds 2000V FCT-C speed at 6.1ns max. Com'l FCT-A speed at 7.0ns max. (Com'l) Matched Rise and Fall times Power-off disable feature
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P54/74FCT399T/AT/CT
FCT399T
MIL-STD-883,
399AT
399CT
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Untitled
Abstract: No abstract text available
Text: P54/74FCT273T/AT/CT OCTAL D FLIP-FLOP FEATURES • Function, Pinout and Drive Compatible with the FCT and F Logic ■ FCT-C speed at 5.8ns max. Com'l FCT-A speed at 7.2ns max. (Com'l) ■ Reduced (typically = 3.3V) versions of Equivalent FCT functions ■ Edge-rate Control Circuitry for Significantly
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P54/74FCT273T/AT/CT
MIL-STD-883,
273AT
273CT
AE1740-3
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PLA 16L8
Abstract: PAL16R8B-4CN Monolithic Memories PAL16R8 TL 2521-2 PALC16R8Q-25 16L8B-2 PAL16R8A-4 16r8a-4 4511 pin configuration 16R6
Text: ADV MICRO 0257526 PLA/PLE/ARRAYS TL. D E § ü 2 5 7 5 2 b 00E70Ö4 96D 2 7 0 8 4 D ADV MI CRO P L A / P L E / A R R A Y S PAL16R8 Family 16 L 8 ,16R8 16 R 6 ,16R4 Ordering Inform ation — Newer Products F eatures/B enefits • Standard 20-pln architectures
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00E70Ã
PAL16R8
20-pln
PAL16R8D
PALC16R8Z
0257526ADV
16III1H
W2S30JI
PLA 16L8
PAL16R8B-4CN
Monolithic Memories PAL16R8
TL 2521-2
PALC16R8Q-25
16L8B-2
PAL16R8A-4
16r8a-4
4511 pin configuration
16R6
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ZD302
Abstract: No abstract text available
Text: 74AC109 • 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop General Description LOW input to C q Clear sets Q to LOW level T h e AC /AC T109 consists of two_ high-speed com pletely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall tim es of th e clock
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74AC109
74ACT109
ZD302
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61S11
Abstract: No abstract text available
Text: fax id: 6016 CY7C331 CYPRESS Asynchronous Registered EPLD Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock in
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28-pin
CY7C331-30DMB
CY7C331-30HMB
CY7C331-30LMB
CY7C331-30QMB
CY7C331--
30TMB
CY7C331-30WMB
CY7C331-40DMB
CY7C331
61S11
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4 bit odd parity checker
Abstract: 0539SA
Text: 906ZUIV Am2906 Quad Two-Input OC Bus Transceiver with Parity DISTINCTIVE CHARACTERISTICS • • • Internal 4-bit odd parity checker/generator. R eceiver has output latch for pipeline operation. R eceiver outputs sink 12 mA. Quad high-speed LSI bus transceiver.
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Am2906
100mA
5398A
0539SA
4 bit odd parity checker
0539SA
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74FCT3574
Abstract: No abstract text available
Text: IDT54/74FCT3574/A ADVANCE INFORMATION 3.3V CMOS OCTAL D REGISTERS 3-STATE Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 0.5 M ICR O N C M O S Technology • ESD > 2000V per M IL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
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IDT54/74FCT3574/A
IL-STD-883,
200pF,
FCT3574/A
IDT54/74FCT3574/3574A
MIL-STD-883,
P20-1
D20-1)
S020-2)
74FCT3574
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Untitled
Abstract: No abstract text available
Text: CY54/74FCT399T QUAD 2-INPUT REGISTERS ^ /C Y P R E S S FEATURES Function, Pinout and Drive Com patible w ith the FCT and F Logic • Pow er-off disable feature ■ M atched Rise and Fall tim es ■ FCT-C speed at 6.1ns max. Com 'l FCT-A speed at 7.0ns max. (Com 'l)
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CY54/74FCT399T
FCT399T
399AT
399CT
MIL-STD-883,
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Untitled
Abstract: No abstract text available
Text: 806ZUIV/Z06ZUIV Am2907/Am2908 Quad Bus Transceivers with Interface Logic DISTINCTIVE CHARACTERISTICS • • • • Quad high-speed LSI bus-transceiver D-type driver register with open-collector bus driver o utput can sink 100mA at O.BV max. Internal 4-bit odd parity checke r/ge n era tor
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Am2907/Am2908
100mA
Am2907
Am2908
WF002370
05399a
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Untitled
Abstract: No abstract text available
Text: P54/74FCT273T/AT/CT OCTAL D FLIP-FLOP FEATURES Fully Compatible with TTL Input and Output Logic Levels 64 mA Sink Current Com’l , 32 mA (Mil) 15 mA Source Current (Com’l), 12 mA (Mil) CMOS for Low-Power Consumption — Typically 1/3 of FAST Bipolar Logic
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P54/74FCT273T/AT/CT
AEI740-3
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Untitled
Abstract: No abstract text available
Text: I lnce3rated Device Technology. Inc HIGH-SPEED CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE IDT54AHCT377 FEATURES: DESCRIPTION: • Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes The IDT54AHCT377 is an octal D flip-flop built using advanced
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IDT54AHCT377
IDT54AHCT377
MIL-STD-883,
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Untitled
Abstract: No abstract text available
Text: 3.3V 128K 8Kx16-BIT CACHE-TAG SRAM For 3.3V Processors PRELIMINARY IDT71V218 Integrated Device Technology, Inc. FEATURES: • 8K x 16 Configuration - 14 Com m on I/O TA G Bits - 2 S eparate I/O Status Bits (VLD and D TY) • Optim ized for 256K B cache and 4G B cacheable space
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8Kx16-BIT)
IDT71V218
48-pin
IDT71V21B
8Kx16
4A25771
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