16C954
Abstract: OX16C952 16C952 Oxford Semiconductor 16c550 16C550 16C950 IEEE1284 OX16C950 OXMPCI952-LQAG
Text: OXmPCI952 DATA SHEET Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface. FEATURES • • • • • • • • • • • • Dual 16C950 High performance UART channels 8-bit Pass-through Local Bus PCI Bridge
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OXmPCI952
16C950
IEEE1284
32-bit,
33MHz,
16C550-type
20MHz
DS-0020
16C954
OX16C952
16C952
Oxford Semiconductor 16c550
16C550
OX16C950
OXMPCI952-LQAG
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TXC10 M 60
Abstract: 10BASE2 10BASE5 93LC46B FPT-144P-M08 MB86961A MB86974 NM93C46
Text: PAUSE FLOW CONTROL 10Mb/s-/100Mb/s Ethernet Controller MB86974 Package • 144-pin, plastic QFP • FPT-144P-M08 Description The Fujitsu MB86974 is a high-quality Ethernet controller that offers many benefits and advantages to its users. The controller operates at either 100-Mbit/s or 10-Mbit/s, and
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10Mb/s-/100Mb/s
MB86974
144-pin,
FPT-144P-M08
MB86974
100-Mbit/s
10-Mbit/s,
LAN-DS-20654-8/98
TXC10 M 60
10BASE2
10BASE5
93LC46B
FPT-144P-M08
MB86961A
NM93C46
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rx2 99
Abstract: 93c46l 93c46li 16C550 AD29 AD30 XR17V258 bu 515 144LQFP 16550
Text: XR17V258 66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT AUGUST 2010 REV. 1.0.2 GENERAL DESCRIPTION The XR17V2581 V258 is a single chip 8-channel 66MHz PCI (Peripheral Component Interconnect) UART (Universal Asynchronous Receiver and Transmitter)
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XR17V258
66MHZ
XR17V2581
32-bit
33MHz
rx2 99
93c46l
93c46li
16C550
AD29
AD30
XR17V258
bu 515
144LQFP
16550
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Untitled
Abstract: No abstract text available
Text: V320USC Universal System Controller • • • • • • PCI System Controller for 32-Bit MIPS and SuperH™ System Interface Device Highlights Introduction • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI
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V320USC
32-Bit
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54SX32
Abstract: A54SX32 A54SX32A A54SX72A PAR64 REQ64 54SX32A il 074
Text: Preliminary v1.0 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce • QML Certified Devices • 215 MHz System Performance Military Temperature • 100% Military Temperature Tested (–55°C and +125°C) • 5.3ns Clock-to-Out (Pin-to-Pin) (Military Temperature)
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AD27
Abstract: AD29 V320USC V320USC-75 AD1485
Text: DS-UC01-0102.fm Page 1 Wednesday, June 30, 1999 7:30 PM Datasheet V320USC Universal System Controller PCI System Controller for 32-Bit MIPS and SuperH™ System Interface • Glueless interface between popular MIPS™ and SuperH™ processors and the standard 32-bit PCI bus
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DS-UC01-0102
V320USC
32-Bit
DS-UC01-0102
AD27
AD29
V320USC-75
AD1485
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TDA 7378
Abstract: TDA 7822 block diagram baugh-wooley multiplier tda 12062 equivalent for tda 4858 ic free transistor equivalent book STD-80 4856 a 14 PIN DIP W908 LSI CMOS Technology
Text: D • A • T • A • B • O • O • K STD80/STDM80 0.5µm 5V/3.3V Standard Cell Library April 1997 V SAMSUNG SAMSUNG ASIC STD80/STDM80 0.5µm 5V/3.3V Standard Cell Library Data Book 1997 Samsung Electronics Co., Ltd. All rights reserved. No part of this document may be reproduced, in any form or by any means, without the prior
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STD80/STDM80
notice10.
TDA 7378
TDA 7822
block diagram baugh-wooley multiplier
tda 12062
equivalent for tda 4858 ic
free transistor equivalent book
STD-80
4856 a
14 PIN DIP W908
LSI CMOS Technology
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ic 74 LS 138 DECODER data sheet
Abstract: 16C550 XR17C154 XR17C158 XR17L154
Text: áç XR17L154 3.3V PCI BUS QUAD UART OCTOBER 2002 REV. 1.0.0 FEATURES GENERAL DESCRIPTION The XR17L1541 L154 is a quad PCI Bus Universal Asynchronous Receiver and Transmitter (UART) with same package and pin-out as the Exar XR17C158 octal UART. The device is designed to meet today’s
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XR17L154
XR17L1541
XR17C158
32-bit
16C550
ic 74 LS 138 DECODER data sheet
XR17C154
XR17C158
XR17L154
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application notes of TF 513
Abstract: PHSOSCK17 PHSOSCK27 STD130
Text: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)
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STD130
application notes of TF 513
PHSOSCK17
PHSOSCK27
STD130
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CL 2181
Abstract: SL 1088 PHSOSCK17 PHSOSCK27
Text: INPUT CLOCK DRIVERS Cell List Cell Name Function Description PSCKDC 2/4/6/8 1.8V CMOS Level Input Clock Driver PSCKDCD(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Down PSCKDCU(2/4/6/8) 1.8V CMOS Level Input Clock Driver with Pull-Up PSCKDS(2/4/6/8)
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STD131
CL 2181
SL 1088
PHSOSCK17
PHSOSCK27
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TDA 9361 PS
Abstract: tda 2974 LD5Q ci 8602 gn block diagram TDA 2265 5.1 AUDIO AMP TDA 2030 TDA 7877 TDA 0200 circuit TDA 9594 TDA 2088
Text: V S MSUNG STD130 ELECTRONICS STD130 Standard Cell 0.18um System-On-Chip ASIC Dec 2000, V2.0 Features 1.8/2.5/3.3V - Leff= 0.15um, Ldrawn = 0.18um Device - Up to 23 million gates - Power dissipation :24nW/MHz 3.3/5.0V - Gate Delay : 48ps @ 1.8V, 1SL Device
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STD130
STD130
24nW/MHz
ARM920T/ARM940T,
TDA 9361 PS
tda 2974
LD5Q
ci 8602 gn block diagram
TDA 2265
5.1 AUDIO AMP TDA 2030
TDA 7877
TDA 0200
circuit TDA 9594
TDA 2088
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HiRel a54sx72a unused
Abstract: No abstract text available
Text: Advanced v1.3 RT54SX-S RadTolerant FPGAs for Space Applications Sp e ci a l F ea t ur es f o r Sp a ce • First Actel FPGA Designed Specifically for Space Applications • Up to 2,012 SEU Hardened Flip-Flops Eliminate Software TMR Necessity LET th > 40, GEO SEU Rate < 10–10
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RT54SX-S
RT54SX-S
TM1019
HiRel a54sx72a unused
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rt54sx32su
Abstract: RTSX72 RTSX32SU RTSX72-S
Text: Advanced v0.1 RTSX-SU RadTolerant FPGAs UMC u e Designed for Space • • • • • SEU-Hardened Registers Eliminate the Need to Implement Triple-Module Redundancy (TMR) – Immune to Single-Event Upsets (SEU) to LETth > 40 MeV-cm2/mg, – SEU Rate < 10–10 Upset/Bit-Day in Worst-Case
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TM1019
rt54sx32su
RTSX72
RTSX32SU
RTSX72-S
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Untitled
Abstract: No abstract text available
Text: M IT S U B IS H I M ICRO CO M PUTERS M 37409P S S PIGGYBACK for M 3 7 4 0 9 M 2 -X X X S P DESCRIPTION FEATURES Th e M 3 7 4 0 9 P S S is an E P R O M m o u n ted -typ e m icrocom pu • te r which utilizes C M O S technology, and is d e s ig n e d for 1
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37409P
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TP2G
Abstract: BPV32 5w100 TOSHIBA MARK C56 CSB503F30 PB001 PB111 TA1310N LF 256H T26G
Text: TOSHIBA TENTATIVE TA1310N TOSHIBA BIPOLAR LINEAR INTEGRATED CIRCUIT SILICON MONOLITHIC T A 1 3 1 ON NTSC VIDEO, CHROMA, DEFRECTION, AND DEC. DISTORTION COMPENSATION IC FOR YUV INTERFACE TA1310N is Video Chroma and defrection signal. Processing IC for NTSC. On a 56-pin shrink DIP package.
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TA1310N
TA131
TA1310N
56-pin
TP13b
TP2G
BPV32
5w100
TOSHIBA MARK C56
CSB503F30
PB001
PB111
LF 256H
T26G
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M37702M4-XXXFP
Abstract: m37702s4bfp M37702M4B
Text: M IT S U B IS H I M IC RO CO M PUTERS M 3 7 7 0 2 M 4 A X X X F P ,M 3 7 7 0 2 M 4 B X X X F P M 3 7 7 0 2 S 4 A F P ,M 3 7 7 0 2 S 4 BF P M l7702S 4FP aÎeF œasnpectively unified into M37702M4AXXXFP and M37702S4AFP. “ , iw a w a m w A h W -w » • ■
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l7702S
M37702M4AXXXFP
M37702S4AFP.
80-pin
16-bit
M37702M4-XXXFP
m37702s4bfp
M37702M4B
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M37450M
Abstract: M37450M8-XXXSP MELPS-740 M37450
Text: M IT S U B IS H I M ICRO CO M PUTERS M 3 7 4 5 0 M 2 -X X X S P /F P ,M 3 7 4 5 0 M 4 -X X X S P /F P M 3 7 4 5 0 M 8 -X X X S P /F P S IN G L E -C H IP 8 -B IT CM O S M IC R O C O M P U T E R DESCRIPTION The M 37450M 2-XX X S P/FP is a s in g le -c h ip m icro com p uter
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37450M
80-pin
M37450M
M37450M8-XXXSP
MELPS-740
M37450
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M37415
Abstract: M37415M4 M37415M4XXXFP M37415M4-XXXFP ara bbc S52H
Text: M IT S U B IS H I M IC RO CO M PUTERS M 37415M 4-XXXFP S IN G L E -C H IP 8 -B IT CMOS M IC R O C O M P U T E R DESCRIPTION PIN CONFIGURATION TOP VIEW The M 37415M 4-XXXFP is a s in g le -c h ip m icro com p uter d e sig n e d w ith C M O S s ilicon ga te technology. It is housed in a
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37415M
M37415
M37415M4
M37415M4XXXFP
M37415M4-XXXFP
ara bbc
S52H
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M37702M8L
Abstract: No abstract text available
Text: M IT S U B IS H I M IC RO CO M PUTERS M 37702M 8LXXXHP S IN G L E -C H IP 1 6-B IT CM O S M IC R O C O M P U T E R DESCRIPTION The M37702M8LXXXHP is a single-chip 16-bit micro computer designed with high-performance CMOS silicon PIN CONFIGURATION TOP VIEW
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37702M
M37702M8LXXXHP
16-bit
80-pin
M37702M8LXXXH)
16VCC,
M37702M8L
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54sx08
Abstract: THERMAL Fuse m20 tf 115 c
Text: v 3 .0 54SX Family FPGAs Leading Edge Performance • 100%Resource Utilization with 100%Pin Locking • 320 MHz Internal Performance • 3.3VOperation with 5.0VInput Tolerance • 3.7 nsClock-to-Out Pi n-to-Pi n • Very Low Power Consumption • 0.1 ns Input Set-Up
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI MICROCOMPUTERS M 37703M 2AXXXSP.M 37703M 2BXXXSP M37703S1ASP,M37703S1BSP M 3 7 7 0 3 M 2 -X X X S P and SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DESCRIPTION PIN CONFIGURATION TOP VIEW T h e M 3 7 7 0 3 M 2 A X X X S P is a sin g le -ch ip m icrocom puter d e
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37703M
M37703S1ASP
M37703S1BSP
16-BIT
P80/C
P77/A
P62/R
20/25ns
25mVrms,
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38002E4SP
Abstract: No abstract text available
Text: M IT S U B IS H I M IC RO CO M PUTERS 3800 Group S IN G L E -C H IP 8 -B IT C M O S M IC R O C O M P U T E R DESCRIPTION FEATURES The 3800 group is the 8-bit microcomputer based on the 740 family core technology. • • The 3800 group is designed for office automation equip
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b24TflEfl
38002E4SP
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Untitled
Abstract: No abstract text available
Text: 54SXFamily FPGAs Leadi ng Edge P e r f o r m a nc e • • 320 MHz Internal Performance • 3.3VOperation with 5.0YInput Tolerance • 3.7 ns Qock-to-Out Pin-to-Pin • • 0.1ns Input Set-Up • Deterministic, Ufcer-Controllable Timing • 0.25 ns d o c k Skew
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54SXFamily
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M37700M
Abstract: No abstract text available
Text: MITSUBISHI MICROCOMPUTERS M 37704M 2A XXXFP M37704M2-XXXFP and M37704S1FP are respectively unified into M37704M2AXXXFP and M37704S1AFP. |U |5 Iw iw 7 7 a a 4 S 1 A F P S IN G L E -C H IP 1 6 -B IT CM O S M IC R O C O M P U T E R DESCRIPTION APPLICATION The M37704M2AXXXFP and M37704S1AFP are single-chip
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37704M
M37704M2-XXXFP
M37704S1FP
M37704M2AXXXFP
M37704S1AFP.
M37704S1AFP
80-pin
25mVrms,
M37700M
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