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    verilog code for serial transmitter

    Abstract: 3.125G verilog prbs generator N1 ASIC
    Text: SERDES Framer Interface Level-5 OIF Compliant SFI-5 Source Synchronous Interface Macro Transmitter Macro Structure Receiver Macro Structure TX Hard Macro n=16 n=15 Up to 3.125Gbps x 17-ch TXOn (n=0-16) n=1 n=0 Data Unit 16:1 MUX RX (Hard Macro) (Soft Macro)


    Original     		125Gbps 17-ch 195Mbps 256-bits 156M-195MHz 622M-781MHz verilog code for serial transmitter 3.125G verilog prbs generator N1 ASIC PDF

    SFI4

    Abstract: sfi4.1 SFI-4 fujitsu lvds standard OC192
    Text: SERDES Framer Interface Level-4 OIF Compliant SFI-4 Source Synchronous Interface Macro ASIC 4 ODT0[3:0] Rx Macro SP 622/780 Mbps x 16ch 4 ODTn[3:0] SP OCKL 1/4 SERDES / Other Devices 622/780 MHz clock Customer Core Logic Tx Macro IDT0[3:0] IDTn[3:0] 4 PS 622/780 Mbps x 16ch


    Original     		16-channel 780Mbps ASIC-FS-20935-6/2002 SFI4 sfi4.1 SFI-4 fujitsu lvds standard OC192 PDF