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    292 CCGA Search Results

    292 CCGA Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    ADC10D1000CCMPR Texas Instruments Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter 376-CCGA 25 Visit Texas Instruments Buy
    ADC10D1000CCMLS Texas Instruments Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter 376-CCGA -55 to 125 Visit Texas Instruments Buy
    ADC12D1600CCMPR Texas Instruments 12-bit, dual 1.6-GSPS or single 3.2-GSPS, RF-sampling analog-to-digital converter (ADC) - aerospace 376-CCGA 25 to 25 Visit Texas Instruments Buy
    ADC12D1620CCMLS Texas Instruments 12-bit, dual 1.6-GSPS or single 3.2-GSPS, RF-sampling analog-to-digital converter (ADC) - aerospace 376-CCGA -55 to 125 Visit Texas Instruments
    ADC12D1600CCMLS Texas Instruments 12-bit, dual 1.6-GSPS or single 3.2-GSPS, RF-sampling analog-to-digital converter (ADC) - aerospace 376-CCGA -55 to 125 Visit Texas Instruments

    292 CCGA Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    Kostat tray

    Abstract: KS-8308 CAMTEX Kostat DAEWON tray 48 DAEWON tray drawing JEDEC Kostat CERAMIC PIN GRID ARRAY CPGA AMD daewon D-12G-56LD-A13
    Text: u Chapter 7 Trays CHAPTER 7 TRAYS Introduction Design and Materials Device Count per Tray and Box Tray Suppliers per Package Type Tray Dimensions Packages and Packing Publication Revision A 3/1/03 7-1 u Chapter 7 Trays INTRODUCTION Trays are used instead of tubes to protect higher


    Original     		PDF and5-741-9148 Kostat tray KS-8308 CAMTEX Kostat DAEWON tray 48 DAEWON tray drawing JEDEC Kostat CERAMIC PIN GRID ARRAY CPGA AMD daewon D-12G-56LD-A13

    Untitled

    Abstract: No abstract text available
    Text: v2 .1  Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


    Original     		PDF 700Mb/s 295kbits

    RTAX1000S

    Abstract: RTAX250S RTAX2000S CCGA CQFP 208 RTAX2000 rtax2000* cqfp 292 CCGA RTAX-S 624 CCGA
    Text: RTAX-S RadTolerant FPGAs Package Pin Assignments 208 207 206 205 160 159 158 157 208-Pin CQFP Pin 1 1 2 3 4 156 155 154 153 Ceramic Tie Bar 208-Pin CQFP 108 107 106 105 101 102 103 104 53 54 55 56 49 50 51 52 Figure 3-1 • 208-Pin CQFP Top View A dv a nc ed v 0. 5


    Original     		PDF 208-Pin RTAX250S IO43PB2F2 IO76PB5F5/CLKGP IO02NB0F0 IO44NB2F2 RTAX1000S RTAX2000S CCGA CQFP 208 RTAX2000 rtax2000* cqfp 292 CCGA RTAX-S 624 CCGA

    CCGA

    Abstract: 938 SO-16 tray datasheet bga LQFP 48 Package Box tray BGA 520 CBF 420 292 CCGA BGA 328 plcc TRAY 40 PIN PDE-208
    Text: u Packing Quantities CHAPTER 6 SUMMARY OF PACKING QUANTITIES Packing Quantities Packages and Packing Publication Revision A 3/1/03 6-1 u Packing Quantities PACKING QUANTITIES The table below summarizes the packing quantities for each package leadcount. The data is sorted first by OPN package code, then by AMD internal package code, and then by lead/ball count. Details on each product carrier can be found in the following chapters:


    Original     		PDF

    RTAX2000S

    Abstract: RTAX1000S-SL cga 624 RTAX1000S RTAX250S RTAX2000 624 CCGA SL D8 E26 RTAX4000S CCGA
    Text: RTAX-S/SL RadTolerant FPGAs Package Pin Assignments 208 207 206 205 160 159 158 157 208-Pin CQFP Pin 1 1 2 3 4 156 155 154 153 Ceramic Tie Bar 208-Pin CQFP 108 107 106 105 101 102 103 104 53 54 55 56 49 50 51 52 Figure 3-1 • 208-Pin CQFP Top View Note


    Original     		PDF 208-Pin RTAX250S/SL IO43PB2F2 IO76PB5F5/CLKGP IO02NB0F0 RTAX2000S RTAX1000S-SL cga 624 RTAX1000S RTAX250S RTAX2000 624 CCGA SL D8 E26 RTAX4000S CCGA

    IO191

    Abstract: Axcelerator Family FPGAs
    Text: v2.3 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


    Original     		PDF

    896-Pin

    Abstract: smartpower IO290 Axcelerator Family FPGAs
    Text: v2.2 Axcelerator Family FPGAs u e Leading-Edge Performance • • • • – 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Specifications • • • • • Up to 2 Million Equivalent System Gates


    Original     		PDF

    icl 2822

    Abstract: 1004CL 0398C BW002 CCGA 472 device dimensional details diode marking B4Z 0844C 4046 PLL Designers Guide AOI2222 2-bit comparator
    Text: Preliminary ASIC Cu-11 Databook Notices: Before using this information and the product it supports, be sure to read the general information on the back cover of this book. Trademarks: The following are trademarks or registered trademarks of International Business Machines


    Original     		PDF Cu-11 SA14-2449-00 icl 2822 1004CL 0398C BW002 CCGA 472 device dimensional details diode marking B4Z 0844C 4046 PLL Designers Guide AOI2222 2-bit comparator

    RTAX2000

    Abstract: RTAX2000S RTAX1000SL rtax250 RTAX250SL RTAX4000SL RTAX1000 RTAX-S RTAX1000S-SL rtax250s
    Text: Rev ision 13 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)


    Original     		PDF TM1019 MIL-STD-883B Extended600 RTAX2000 RTAX2000S RTAX1000SL rtax250 RTAX250SL RTAX4000SL RTAX1000 RTAX-S RTAX1000S-SL rtax250s

    729-Pin

    Abstract: Axcelerator FPGAs AX125 IO126PB3F11 AG18 FBGA 896 896-Pin Axcelerator Family FPGAs
    Text: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View Note For Package Manufacturing and Environmental information, visit Resource center at


    Original     		PDF 180-Pin AX125 IO32NB3F3 IO59NB5F5 729-Pin Axcelerator FPGAs IO126PB3F11 AG18 FBGA 896 896-Pin Axcelerator Family FPGAs

    AX125

    Abstract: FBGA 896 896-Pin
    Text: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View Note For Package Manufacturing and Environmental information, visit Resource center at


    Original     		PDF 180-Pin AX125 IO32NB3F3 IO59NB5F5 FBGA 896 896-Pin

    CCGA

    Abstract: 896-Pin 624 CCGA AD 149 AE9 FBGA 63 AX125 FBGA 896
    Text: Axcelerator Family FPGAs Package Pin Assignments 180-Pin CSP A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P Figure 3-1 • 180-Pin CSP Bottom View v2.3 3-1 Axcelerator Family FPGAs 180-Pin CSP 180-Pin CSP AX125 Function Pin Number


    Original     		PDF 180-Pin AX125 IO32NB3F3 IO59NB5F5 CCGA 896-Pin 624 CCGA AD 149 AE9 FBGA 63 FBGA 896

    RTAX2000

    Abstract: rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3
    Text: v5.1 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg


    Original     		PDF TM1019 RTAX2000 rtax4000 CDB 455 C34 IO358 DIODE SMD V05 128X3

    CQ352-FPGA

    Abstract: RTAX1000s-cq RTAX4000S RTAX2000 RTAX2000S-CQ352 FPGA Application Note schematic 324 CDB 455 C34 rtax4000 AP3433
    Text: v4.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case


    Original     		PDF TM1019 CQ352-FPGA RTAX1000s-cq RTAX4000S RTAX2000 RTAX2000S-CQ352 FPGA Application Note schematic 324 CDB 455 C34 rtax4000 AP3433

    RTAX250

    Abstract: RTAX4000DL RTAX4000D CG624 RTAX4000S LG1152 TRANSISTOR TB 772 SL RTAX2000S ACTEL CCGA 624 mechanical transistor prc 606 j
    Text: Revision 15 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)


    Original     		PDF TM1019 RTAX250 RTAX4000DL RTAX4000D CG624 RTAX4000S LG1152 TRANSISTOR TB 772 SL RTAX2000S ACTEL CCGA 624 mechanical transistor prc 606 j

    Untitled

    Abstract: No abstract text available
    Text: Revision 16 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)


    Original     		PDF TM1019 MIL-STD-883B

    w32 smd transistor

    Abstract: rtax250sl RTAX2000S w32 smd transistor 143 41-bit Carry Look-ahead Adder RTAX2000SL RTAX4000S BY415 RTAX4000D LG1152
    Text: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)


    Original     		PDF TM1019 MIL-STD-883B w32 smd transistor rtax250sl RTAX2000S w32 smd transistor 143 41-bit Carry Look-ahead Adder RTAX2000SL RTAX4000S BY415 RTAX4000D LG1152

    RTAX2000D

    Abstract: LG1152 CDB 455 C34
    Text: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)


    Original     		PDF TM1019 RTAX2000D LG1152 CDB 455 C34

    624 CCGA

    Abstract: CQ352 transistor prc 606 j rtax250 RTAX2000 rtax4000
    Text: Revision 14 RTAX-S/SL and RTAX-DSP Radiation-Tolerant FPGAs Radiation Performance Specifications • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeVcm2/mg – SEU Rate < 10-10 Errors/Bit-Day (worst case GEO)


    Original     		PDF TM1019 624 CCGA CQ352 transistor prc 606 j rtax250 RTAX2000 rtax4000

    RTAX2000S

    Abstract: CDB 455 C34 RTAX1000S-CQ352 RTAX2000S-CQ352
    Text: v3.0 RTAX-S RadTolerant FPGAs Designed for Space • • • • • • • • SEU-Hardened Registers Eliminate the Need for Triple-Module Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg – SEU Rate < 10-10 Errors/Bit-Day in Worst-Case


    Original     		PDF TM1019 RTAX2000S CDB 455 C34 RTAX1000S-CQ352 RTAX2000S-CQ352

    LGA 478 SOCKET PIN LAYOUT

    Abstract: RTAX2000
    Text: v5.2 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg


    Original     		PDF TM1019 LGA 478 SOCKET PIN LAYOUT RTAX2000

    Untitled

    Abstract: No abstract text available
    Text: Standard Products UT699 32-bit Fault-Tolerant SPARCTM V8/LEON 3FT Processor Data Sheet June 25, 2012 INTRODUCTION FEATURES  Implemented on a 0.25mCMOS technology  Flexible static design allows up to 66MHz clock rate  89 DMIPS throughput via 66MHz base clock frequency


    Original     		PDF UT699 32-bit 66MHz IEEE-754 352-Ceramic 484-Ceramic UT699 -40oC

    Synplify tmr

    Abstract: 2965A ACTEL CCGA 1152 mechanical RTAX2000 CGS624 A54SX16 TM-3015 CCGA RTAX1000S-SL rtax250s
    Text: v5.3 RTAX-S/SL RadTolerant FPGAs Radiation Performance Leading-Edge Performance • • • • • • • • • • SEU-Hardened Registers Eliminate the Need for TripleModule Redundancy TMR – Immune to Single-Event Upsets (SEU) to LETTH > 37 MeV-cm2/mg


    Original     		PDF TM1019 Synplify tmr 2965A ACTEL CCGA 1152 mechanical RTAX2000 CGS624 A54SX16 TM-3015 CCGA RTAX1000S-SL rtax250s

    SPARC v8 architecture BLOCK DIAGRAM

    Abstract: 352-CQFP
    Text: Standard Products UT699 32-bit Fault-Tolerant SPARCTM V8/LEON 3FT Processor Data Sheet June 25, 2012 INTRODUCTION FEATURES  Implemented on a 0.25mCMOS technology  Flexible static design allows up to 66MHz clock rate  89 DMIPS throughput via 66MHz base clock frequency


    Original     		PDF UT699 32-bit 25mCMOS 66MHz IEEE-754 SPARC v8 architecture BLOCK DIAGRAM 352-CQFP