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    Luminus Devices XBT-3535-UV-A130H-M-BC270-00

    XBT-3535-UV SURFACE MOUNT UVC L
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    DigiKey XBT-3535-UV-A130H-M-BC270-00 Digi-Reel 250 1
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    XBT-3535-UV-A130H-M-BC270-00 Cut Tape 250 1
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    XBT-3535-UV-A130H-M-BC270-00 Reel 250
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    Avnet Americas XBT-3535-UV-A130H-M-BC270-00 Reel 8 Weeks 250
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    Mouser Electronics XBT-3535-UV-A130H-M-BC270-00 250
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    EBV Elektronik XBT-3535-UV-A130H-M-BC270-00 9 Weeks 250
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    Rochester Electronics LLC CY7C341-30HMB

    UV PLD, 59NS, 192-CELL CQCC84
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    DigiKey CY7C341-30HMB Bulk 1
    • 1 $598.59
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    Teledyne e2v CY7C342B-30HMB

    CPLD, UV ERASABLE, 128-MACROCELL, 30 NS - Trays (Alt: CY7C342B-30HMB)
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    Teledyne e2v CY7C343-30HMB

    EPLD, 64-MACROCELL - Trays (Alt: CY7C343-30HMB)
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    Teledyne e2v CY7C346-30HMB

    CPLD, UV ERASABLE, 128-MACROCELL, 30 NS - Trays (Alt: CY7C346-30HMB)
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    Find more 30HMB price and stock on Findchips.com

    30HMB Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    transistor c331

    Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
    Text: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the


    Original     		PDF CY7C331 CY7C331 transistor c331 c331 transistor C3318 C3317 C331 C3311 C331 datasheet 20HC c331 equivalent

    CY7C342B

    Abstract: 68-PIN CY7C342B-35RMB
    Text: fax id: 6107 1CY 7C34 2B CY7C342B 128-Macrocell MAX EPLDs Features The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB.


    Original     		PDF CY7C342B 128-Macrocell CY7C342B 65-micron 68-pin CY7C342B-35RMB

    c3466

    Abstract: C3461 C3467 b4 c346 diode c346 diode IC 7400 SERIES ALL DATA C346 CY7C346 CY7C346B c3468
    Text: fax id: 6104 1CY 7C34 6B CY7C346 CY7C346B 128-Macrocell MAX EPLDs Features ture is 100% user configurable, allowing the devices to accommodate a variety of independent logic functions. • • • • 128 macrocells in 8 LABs 20 dedicated inputs, up to 64 bidirectional I/O pins


    Original     		PDF CY7C346 CY7C346B 128-Macrocell CY7C346) 65-micron CY7C346B) 84-pin 100-pin CY7C346/CY7C346B c3466 C3461 C3467 b4 c346 diode c346 diode IC 7400 SERIES ALL DATA C346 CY7C346 CY7C346B c3468

    CY7C342B

    Abstract: 7C342B-35 68-PIN CY7C342B15HMB CY7C342B-35RMB CY7C342B-35HC
    Text: 1CY 7C34 2B CY7C342B 128-Macrocell MAX EPLDs Features The 128 macrocells in the CY7C342B are divided into 8 Logic Array Blocks LABs , 16 per LAB. There are 256 expander product terms, 32 per LAB, to be used and shared by the macrocells within each LAB.


    Original     		PDF CY7C342B 128-Macrocell CY7C342B 65-micron 68-pin 68-Lead 7C342B-35 CY7C342B15HMB CY7C342B-35RMB CY7C342B-35HC

    transistor c331

    Abstract: c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet
    Text: fax id: 6016 1CY7C331 CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable


    Original     		PDF 1CY7C331 CY7C331 transistor c331 c331 transistor c331 c331 equivalent C3318 C3319 C3314 c3317 C3311 transistor c331 datasheet

    31-oq

    Abstract: 7C342-25 CY7C342-35HMB 7C342-35 CY7C342 CY7C342B OQ11
    Text: CY7C342 CY7C342B rif CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342


    OCR Scan     		PDF CY7C342 CY7C342B 128-Macrocell CY7C342) 65-micron CY7C342B) 68-pin CY7C342/CY7C342B CY7C342/ CY7C342B 31-oq 7C342-25 CY7C342-35HMB 7C342-35 OQ11

    84-PIN

    Abstract: CY7C341B
    Text: CY7C341B y CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pin • Advanced 0.65-micron CMOS technology to increase performance • Programmable interconnect array • 384 expander product terms • Available in 84-pin HLCC, PLCC, and


    OCR Scan     		PDF CY7C341B 65-micron 84-pin CY7C341B CY7C341Bis 35RC/RI 84-Lead CY7C341Bâ 35HMB

    L496D

    Abstract: 9l reset CY7C331 ST L11922 0423-J
    Text: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,


    OCR Scan     		PDF CY7C331 28-pin CY7C331 -40TMB 28-Lead CY7C331â 40WMB 28-Lead 300-Mil) L496D 9l reset ST L11922 0423-J

    K12J

    Abstract: 100-PIN CY7C346 CY7C346B f 7400
    Text: CY7C346 CY7C346B 5T CYPRESS 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, up to 64 bidirec­ tional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346


    OCR Scan     		PDF CY7C346 CY7C346B CY7C346) 65-micron CY7C346B) 84-pin 100-pin 128-Macrocell CY7C346/CY7C346B CY7C346/ K12J CY7C346B f 7400

    Untitled

    Abstract: No abstract text available
    Text: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin


    OCR Scan     		PDF 28-pin 28-pin termW22 28-Lead 300-Mil) CY7C331 001305b

    CY7C276-25JC

    Abstract: CY7C276 C2768 tCKA
    Text: CY7C276 CYPRESS SEMICONDUCTOR Features • 0.8-micron CMOS for optimum speed/ power • High speed for commercial and military — 25-ns access time • • • • 16-bit-wide words Three programmable chip selects Programmable output enable 44-pin PLCC and 44-pin LCC


    OCR Scan     		PDF CY7C276 25-ns 16-bit-wide 44-pin CY7C276 16K-word 16-bit CY7C276-25JC C2768 tCKA

    C3424

    Abstract: 68-PIN 7C342-30 7C342-35 CY7C342 CY7C342B C3422 CY7C342-30HC CY7C342B-30RMB 30RM
    Text: CY7C342 CY7C342B CYPRESS 128-Macrocell MAX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342


    OCR Scan     		PDF CY7C342 CY7C342B 128-Macrocell CY7C342) 65-micron CY7C342B) 68-pin CY7C342/CY7C342B CY7C342/ C3424 7C342-30 7C342-35 C3422 CY7C342-30HC CY7C342B-30RMB 30RM

    TAC01

    Abstract: No abstract text available
    Text: CY7C343 CYPRESS SEMICONDUCTOR 64-Macrocell MAX EPLD F eatures F unctional D escription • 64 MAX macrocells in 4 LABs The CY7C343 is a high-performance, high-density erasable programmable logic device, available in 44-pin PLCC and HLCC packages. The CY7C343 contains 64 highly flexible


    OCR Scan     		PDF CY7C343 44-pin 64-Macrocell CY7C343 CY7C343-- 30HC/HI CY7C343-30JC/JI TAC01

    C3317

    Abstract: L1190 CY7331
    Text: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all


    OCR Scan     		PDF 28-pin 28-Lead 28-Lead 300-Mil) CY7C331 0Dlb56b C3317 L1190 CY7331

    CY7C342

    Abstract: No abstract text available
    Text: CY7C342 CYPRESS SEMICONDUCTOR 128-Macrocell MAX EPLDs The speed and density of the CY7C342 allows it to be used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips. With greater than 25 times the


    OCR Scan     		PDF CY7C342 128-Macrocell 7400-series 20-pin CY7C342

    C2704

    Abstract: No abstract text available
    Text: Revision: Tuesday, January 5,1993 CY7C270 CYPRESS — :. SEMICONDUCTOR • 100% reprogrammable in windowed packages • TTL-compatible I/O • Capable of withstanding greater than 2001V static discharge Features • 0.8-micron CMOS for optimum speed/power


    OCR Scan     		PDF CY7C270 25-ns 11-ns 16-bit-wide 44-pin CY7C270 16K-word 16-bit C2704

    C2723

    Abstract: C272-3
    Text: CY7C272 PRELIMINARY = ¡ ^ 5 sr s c y p r e s s 1 SEMICONDUCTOR Features • 0.8-micron CMOS for optimum speed/ power • High speed — 25 ns max set-up — 25 ns clock to output • 16-bit-wide words • Registered outputs • Programmable synchronous or


    OCR Scan     		PDF CY7C272 16-bit-wide 40-pin, 600-mil-wide 44-pin CY7C272 16K-word 16-bit It272â C2723 C272-3

    Untitled

    Abstract: No abstract text available
    Text: CY7C346 CY7C346B CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 20 dedicated inputs, 64 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C346


    OCR Scan     		PDF CY7C346 CY7C346B 128-Macrocell CY7C346/CY7C346B of7400-series 20-pin CY7C346/ CY7C346B

    Untitled

    Abstract: No abstract text available
    Text: CY7C276 '0 C Y P R E S S 16Kx 16 Reprogrammable PROM Functional Description The CY7C276 allows the user to indepen­ dently program the polarity of each chip select CS2- C S 0 . This provides on-chip decoding of up to eight banks of PROM. The polarity of the asynchronous output


    OCR Scan     		PDF CY7C276 CY7C276 16Kword 16-bit 44-pin 44-pin CY7C276, CY7C276â

    CY7C332-25HMB

    Abstract: L9646 c3328 L9806 l9634 L9680 L480 L9622 L9626 L9823
    Text: CY7C332 '0 C Y P R E S S F e a tu re s • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product terms (PTs) per output — Product terra (PT) output polarity


    OCR Scan     		PDF CY7C332 CY7C332â 30LMB 28-Square 30TMB 28-Lead 30WMB 28-Lead CY7C332-25HMB L9646 c3328 L9806 l9634 L9680 L480 L9622 L9626 L9823

    tsl-3

    Abstract: gear 49t 7C341-40 CY7C341 CY7C341B 38-00137-F 7C341 dd1307h
    Text: CY7C341 CY7C341B if CYPRESS Features • 192 macrocells in 12 LABs • 8 dedicated inputs, 64 bidirectional I/O pins • 0.8-micron double-metal CMOS EPROM technology CY7C341 • Advanced 0.65-micron CMOS technology to increase performance (CY7C341B) • Programmable interconnect array


    OCR Scan     		PDF CY7C341 CY7C341B 192-Macrocell CY7C341) 65-micron CY7C341B) 84-pin TheCY7C341 andCY7C341Bare CY7C341/ tsl-3 gear 49t 7C341-40 CY7C341B 38-00137-F 7C341 dd1307h

    G013G

    Abstract: 05V3 7C342-30 7C342-35 CY7C342 CY7C342B CY7C342-30RMB K941 12J8 CY7C342-35JC
    Text: CY7C342 CY7C342B ^ CYPRESS 128-Macrocell M AX EPLD Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology CY7C342


    OCR Scan     		PDF CY7C342 CY7C342B 128-Macrocell CY7C342) 65-micron CY7C342B) 68-pin CY7C342/CY7C342B CY7C342/ G013G 05V3 7C342-30 7C342-35 CY7C342-30RMB K941 12J8 CY7C342-35JC

    CY7C342-35RMB

    Abstract: CY7C342-30HC CY7C342 CY7C342B 4s44 CY7C342-30RMB 7C342-30
    Text: fc.SE D CYPRESS SEMICONDUCTOR • SSôTbhE 0D1D4Û0 41Ô * C Y P CY7C342 CY7C342B :s CYPRESS SEMICONDUCTOR 128-Macrocell MAX EPLDs Features Functional Description • 128 macrocells in 8 LABs • 8 dedicated inputs, 52 bidirectional I/O pins • Programmable interconnect array


    OCR Scan     		PDF CY7C342 CY7C342B 128-Macrocell 68-pin CY7C342/CY7C342B CY7C342/ CY7C342Bâ 25RMB CY7C342-35RMB CY7C342-30HC 4s44 CY7C342-30RMB 7C342-30

    2SUR

    Abstract: CY7C331 L1190 C3317
    Text: CY7C331 ¿F C Y P R E S S Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set, reset, and clock inpnts on all


    OCR Scan     		PDF CY7C331 28-pin 40HMB CY7C331â 40LMB 28-Square 40QMB 2SUR L1190 C3317