TTL 74-series IC
Abstract: 74ACT280 74ACT280B 74ACT280M AC280
Text: 74ACT280 9 BIT PARITY GENERATOR/CHECKER • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4 ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50Ω TRANSMISSION LINE DRIVING
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74ACT280
AC280
TTL 74-series IC
74ACT280
74ACT280B
74ACT280M
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74ACT280MTR
Abstract: 74ACT280TTR TSSOP14 74ACT280 74ACT280B 74ACT280M
Text: 74ACT280 9 BIT PARITY GENERATOR/CHECKER • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 7ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
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74ACT280
74ACT280
74ACT280MTR
74ACT280TTR
TSSOP14
74ACT280B
74ACT280M
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PDF
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74ACT280
Abstract: 74ACT280B 74ACT280M 74ACT280MTR 74ACT280TTR TSSOP14
Text: 74ACT280 9 BIT PARITY GENERATOR/CHECKER • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 7ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), V IL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
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74ACT280
74ACT280
74ACT280B
74ACT280M
74ACT280MTR
74ACT280TTR
TSSOP14
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PDF
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TTL 74-series IC
Abstract: 74ACT280 74ACT280B 74ACT280M 74ACT280MTR 74ACT280TTR TSSOP14
Text: 74ACT280 9 BIT PARITY GENERATOR/CHECKER • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 7ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), V IL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING
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Original
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74ACT280
74ACT280
TTL 74-series IC
74ACT280B
74ACT280M
74ACT280MTR
74ACT280TTR
TSSOP14
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PDF
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SN64BCT657
Abstract: No abstract text available
Text: SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SCBS090A – NOVEMBER 1991 – REVISED JANUARY 1994 • • • • • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V
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SN64BCT657
SCBS090A
MIL-STD-883C,
300-mil
SN64BCT657
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PDF
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application of parity checker
Abstract: SN64BCT657
Text: SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SCBS090A – NOVEMBER 1991 – REVISED JANUARY 1994 • • • • • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V
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Original
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SN64BCT657
SCBS090A
MIL-STD-883C,
300-mil
application of parity checker
SN64BCT657
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PDF
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4 bit even parity generator circuit
Abstract: 4 bit even and odd parity checker truth table PLS153 SU-210 PLS153A AN021 application of parity checker
Text: Philips Semiconductors Programmable Logic Devices Application Note 9-Bit parity generator/checker with PLS153/153A AN021 INTRODUCTION This application note presents the design of a parity generator using Philips Semiconductors PLD, PLS153 or PLS153A, which enables the designers to customize
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PLS153/153A
AN021
PLS153
PLS153A,
4 bit even parity generator circuit
4 bit even and odd parity checker truth table
SU-210
PLS153A
AN021
application of parity checker
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PDF
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SN64BCT657
Abstract: SN64BCT657DW SN64BCT657NT
Text: SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SCBS090A – NOVEMBER 1991 – REVISED JANUARY 1994 • • • • • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V
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Original
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SN64BCT657
SCBS090A
MIL-STD-883C,
300-mil
SN64BCT657
SN64BCT657DW
SN64BCT657NT
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PDF
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SN64BCT657
Abstract: No abstract text available
Text: SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3ĆSTATE OUTPUTS SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994 • • • • • DW OR NT PACKAGE TOP VIEW State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per
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Original
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SN64BCT657
SCBS090A
MIL-STD-883C,
300-mil
SN64BCT657
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PDF
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SN64BCT657
Abstract: No abstract text available
Text: SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3ĆSTATE OUTPUTS SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994 • • • • • DW OR NT PACKAGE TOP VIEW State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per
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Original
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SN64BCT657
SCBS090A
MIL-STD-883C,
300-mil
SN64BCT657
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PDF
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Untitled
Abstract: No abstract text available
Text: Ü7E D I b¡E!4l iñ27 D Q m i T q MITSUBISHI ADVANCED SCHOTTKY TTL , M 7 4 F 2 80P /FP /D P MITSUBISHI -CDGTL LOGIC} 07E D r 9 -B IT ODD/EVEN PARITY GENERATOR/CHECKER 7 DESCRIPTION The M74F280P is a semiconductor integrated circuit containing a 9-bit parity generator/checker.
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M74F280P
74F280P/FP/PP
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g0517
Abstract: No abstract text available
Text: NATIONAL SEMICOND {LOGIC* t,l SEMICONDUCTOR 61C 5 1 7 2 4 7- 4 5 - / ? - g g National À jà Semiconductor PRELIM" DM54AS280/DM74ÀS280 9-Bit Parity Generator/Checker General Description These universal, 9-bit parity generators/checkers utilize •
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DM54AS280/DM74AS280
DM54AS280/DM74
AS280
bS01122
005172b
DM54AS280/
DM74AS280
TU/F/6303-2
AS280s
g0517
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PDF
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Untitled
Abstract: No abstract text available
Text: 54ACT11853, 74ACT11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS T I0 1 77— 0 3 4 7 4 , MARCH 1090 54ACT11853 . - JT PACKAGE 74ACT11853 . DW or NT PACKAGE TOP VIEW • Inputs are TTL-Voltage Compatible • High-Speed Bus Transceivers with Parity Generator/Checker
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54ACT11853,
74ACT11853
500-mA
300-mil
ACT11853
TI0177--
D3474,
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Untitled
Abstract: No abstract text available
Text: 54AC11833, 74AC11833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS T 10165— D 3448, MARCH 1990 High-Speed Bus Transceivers with Parity Generator/Checker 5 4A C 11 8 33 . . . J T P ACKA G E 7 4 A C 11833 . . . D W OR N T P ACKA G E TO P V IE W Parity-Error Flag Open-Draln Output
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54AC11833,
74AC11833
500-mA
300-mll
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Untitled
Abstract: No abstract text available
Text: M MOTOROLA M ilita ry 5 4 L S 2 8 0 9-B it Odd/Even P arity G en erato r/C h ecker MPO ELECTRICALLY TESTED PER: MIL-M-38510/32901 The 54LS280 is a Universal 9-Bit Parity Generator/Checker. It features odd/even outputs to facilitate either odd or even parity. By
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MIL-M-38510/32901
54LS280
LS280
LS180
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Untitled
Abstract: No abstract text available
Text: M MOTOROLA M ilita ry 5 4 L S 2 8 0 9 -B it Odd/Even P arity G en erato r/C h ecker MPO uiliu ELECTRICALLY TESTED PER: MIL-M-38510/32901 The 54LS280 is a Universal 9-Bit Parity Generator/Checker. It features odd/even outputs to facilitate either odd or even parity. By
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MIL-M-38510/32901
54LS280
LS280
LS180
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PDF
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Untitled
Abstract: No abstract text available
Text: 74ACT280 9 BIT PARITY GENERATOR/CHECKER . HIGH SPEED: tpD =4 ns TYP. at Vcc =5V • LOW POWER DISSIPATION: Icc = 4 |oA (MAX.) at T a = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN), V il = 0.8V(MAX) . 50i2 TRANSMISSION LINE DRIVING CAPABILITY . SYMMETRICAL OUTPUT IMPEDANCE:
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74ACT280
74ACT280B
74ACT280M
AC280
SO-14
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PDF
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Untitled
Abstract: No abstract text available
Text: M M O T O R O L A SN54LS280 SN74LS280 D E S C R I P T I O N — The S N 5 4 L S / 7 4 L S 2 8 0 is a Universal 9-Bit Parity Generator/Checker. It features odd/even outputs to facilitate either odd or even parity. By cascading, the word length is easily expanded.
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dba options me
Abstract: No abstract text available
Text: SN74ALS29833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D2990, F E B R U A R Y 1987 - R EV ISED O C T O B E R 1991 I • Functionally Similar to AMD Am29833 I I • High-Speed Bus Transceivers with Parity Generator/Checker | S N 7 4 A L S '. . . D W O R N T P A C K A G E
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SN74ALS29833
D2990,
Am29833
ALS29833)
300-mil
dba options me
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PDF
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MC10177
Abstract: MC10216 MC10194 MC10170 MC10171 MC10172 MC10173 MC10175 MC10176 MC10178
Text: Function 9 — 2-Bit Parity Generator-Checker Dual Binary to 1-4 Decoder Low Dual Binary to 1-4 Decoder (High) Quad 2-Input Multiplexer/Latch Dual 4 to 1 Multiplexer Q uint Latch Hex " D " Master-Slave Flip-Flop Triple M E C L to N M O S Translator Binary Counter
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MC3461
MC10177
MC10177
MC10216
MC10194
MC10170
MC10171
MC10172
MC10173
MC10175
MC10176
MC10178
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74180
Abstract: 74180 parity generator 4 bit even and odd parity checker 74180 parity 74180 bit 93180 8284 pin diagram 8284 ScansUX987
Text: TTL/MSI 93180/54180. 74180 8-BIT PARITY GENERATOR/CHECKER D E S C R IP T IO N — T h e 9 3 1 8 0 /5 4 1 8 0 or 7 4 1 8 0 are m ono lith ic, 8 -B it Parity Check/Generators which L O G IC S Y M B O L , feature control inputs and even/odd outputs to enhance operation in either odd or even parity
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The93180/54180or
74180
74180 parity generator
4 bit even and odd parity checker
74180 parity
74180 bit
93180
8284 pin diagram
8284
ScansUX987
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PDF
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Untitled
Abstract: No abstract text available
Text: Technical Data _ CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker V cc"4 Type Features: • B uffered inputs u Typical propagation delay: 10 ns @ V Cc = 5 V, T, = 25°C, CL = 50 pF GND- 7 FUNCTIONAL DIAGRAM The RCA CD54/74AC280 and CD54/74ACT280 9 -b it o d d /
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CD54/74AC280
CD54/74ACT280
CD54/74AC280
CD54/74ACT280
CD54/74AC
CD54/74ACT
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PDF
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74ac280
Abstract: No abstract text available
Text: T e c h n ic a l D a la - . . CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker X CVCN t 01» NC.3 Vç ç 9 2 CS-5M H » 4 ONO» T Type Features: • Buffered inputs m Typical propagation delay: 10 ns @ Vcc = 5 V, U = 25° C, C l = 50 pF FUNCTIONAL DIAGRAM
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CD54/74AC280
CD54/74ACT280
CD54/74ACT280
CD54/74AC
CD54/74ACT
74ac280
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PDF
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74LS family
Abstract: 74HC MM54HC MM54HC280 MM74HC MM74HC280
Text: January 1988 Semiconductor MM54HC280/MM74HC280 9-Bit Odd/Even Parity Generator/Checker General Description Features The M M 5 4H C 28 0 /M M 7 4 H C 2 80 utilizes advanced silico n gate C M OS te ch n olo gy to achieve th e high noise im m unity and low pow e r consum ption o f standard C M OS integrated
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MM54HC280/MM74HC280
MM54HC280/MM74HC280
54HC/74HC
54LS/74LS
74LS family
74HC
MM54HC
MM54HC280
MM74HC
MM74HC280
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