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    4-PIN SOP THETA JC VALUE Search Results

    4-PIN SOP THETA JC VALUE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    TPH9R00CQH Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 150 V, 64 A, 0.009 Ohm@10V, SOP Advance / SOP Advance(N) Visit Toshiba Electronic Devices & Storage Corporation
    TPH9R00CQ5 Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 150 V, 64 A, 0.009 Ω@10 V, High-speed diode, SOP Advance / SOP Advance(N) Visit Toshiba Electronic Devices & Storage Corporation
    TPH1R306PL Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 60 V, 100 A, 0.00134 Ω@10 V, SOP Advance / SOP Advance(N) Visit Toshiba Electronic Devices & Storage Corporation
    TPHR8504PL Toshiba Electronic Devices & Storage Corporation N-ch MOSFET, 40 V, 150 A, 0.00085 Ω@10 V, SOP Advance / SOP Advance(N) Visit Toshiba Electronic Devices & Storage Corporation
    TPH2R408QM Toshiba Electronic Devices & Storage Corporation MOSFET, N-ch, 80 V, 120 A, 0.00243 Ohm@10V, SOP Advance Visit Toshiba Electronic Devices & Storage Corporation

    4-PIN SOP THETA JC VALUE Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    PL123E-09HSC

    Abstract: 16-Pin TSSOP theta Jc value PL123E-09 PL123E-09OC P123E-09 P123E09H
    Text: PL123E-09 Preliminary Low Skew Zero Delay Buffer FEATURES DESCRIPTION • • • • The PL123E-09 (-09H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has two lowskew output banks, of 4 outputs each, that are synchronized with the input. Control of the two banks of


    Original     		PL123E-09 10MHz 220MHz PL123E-09H 16-Pin PL123E-09HSC 16-Pin TSSOP theta Jc value PL123E-09 PL123E-09OC P123E-09 P123E09H PDF

    16-Pin TSSOP theta Jc value

    Abstract: No abstract text available
    Text: Preliminary PL123E-08 2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output Zero Delay Buffer FEATURES DESCRIPTION • The PL123E-08 is a PLL-based zero-delay buffer family, used to distribute up to eight outputs. Select inputs S2 and S1 control the state of the two output banks.


    Original     		PL123E-08 PL123E-08 16-Pin TSSOP theta Jc value PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary PL123E-04 2.5V or 3.3V, 10-220 MHz, Low Jitter, 4-Output Zero Delay Buffer FEATURES DESCRIPTION • The PL123E-04 is a PLL-based zero-delay buffer, used to distribute up to four outputs. An external feedback pin enables removing delay from external components.


    Original     		PL123E-04 PL123E-04 PDF

    PL123E-05SC

    Abstract: No abstract text available
    Text: Preliminary PL123E-05 Low Skew Zero Delay Buffer FEATURES DESCRIPTION • • • • The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has five lowskew outputs that are synchronized with the input. The


    Original     		PL123E-05 100ps, 10MHz 220MHz PL123E-05h PL123E-05SC PDF

    P123E05

    Abstract: No abstract text available
    Text: Preliminary Low Skew Zero Delay Buffer FEATURES DESCRIPTION •    The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has five lowskew outputs that are synchronized with the input. The


    Original     		PL123E-05 100ps, 10MHz 220MHz PL123th P123E05 PDF

    P123E09H

    Abstract: PL123E-09 PL123E-09HSC
    Text: Preliminary Low Skew Zero Delay Buffer FEATURES DESCRIPTION •    The PL123E-09 (-09H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has two lowskew output banks, of 4 outputs each, that are synchronized with the input. Control of the two banks of


    Original     		PL123E-09 10MHz 220MHz PL123E-09H 16-Pin P123E09H PL123E-09 PL123E-09HSC PDF

    Untitled

    Abstract: No abstract text available
    Text: PL123E-09 Preliminary Low Skew Zero Delay Buffer FEATURES DESCRIPTION Frequency Range 10MHz to 220MHz Zero input - output delay. Low Output to Output Skew Optional Drive Strength: Standard (8mA) PL123E-09 High (12mA) PL123E-09H 2.5V or 3.3V, ±10% operation.


    Original     		PL123E-09 10MHz 220MHz PL123E-09 PL123E-09H 16-Pin CA95134 PDF

    Untitled

    Abstract: No abstract text available
    Text: PL123E-09 Preliminary Low Skew Zero Delay Buffer DESCRIPTION FEATURES Frequency Range 10MHz to 220MHz Zero input - output delay. Low Output to Output Skew Optional Drive Strength: Standard (8mA) PL123E-09 High (12mA) PL123E-09H 2.5V or 3.3V, ±10% operation.


    Original     		PL123E-09 10MHz 220MHz PL123E-09H 16-Pin CA95134 PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary PL123E-05 Low Skew Zero Delay Buffer FEATURES DESCRIPTION •    The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer d esigned to distribute high speed clocks. It has five low-skew outputs that are synchronized with the input. The sy nchronization is established via CLKOUT feed back to


    Original     		PL123E-05 10MHz 220MHz PL123E-05 PL123E-05H 100ps, PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary PL123E-05 Low Skew Zero Delay Buffer DESCRIPTION FEATURES The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has five low-skew outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to


    Original     		PL123E-05 100ps, 10MHz 220MHz PL123E CA95134 PDF

    Untitled

    Abstract: No abstract text available
    Text: Preliminary PL123E-05 Low Skew Zero Delay Buffer FEATURES DESCRIPTION The PL123E-05 (-05H for High Drive) is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks. It has five low-skew outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to


    Original     		PL123E-05 10MHz 220MHz PL123E-05 PL123E-05H 100ps, CA95134 PDF

    ps 0800

    Abstract: PL123E-09HSC-R PL123E-09HSC
    Text: PL123E-09 Preliminary Low Skew Zero Delay Buffer FEATURES DESCRIPTION •    The PL123E-09 (-09H for High Drive) is a high performance, low skew, low jitter zero delay buffer d esigned to distribute high speed clocks. It has two low-skew output banks, of 4 outputs each, that are synchronized


    Original     		PL123E-09 10MHz 220MHz PL123E-09 PL123E-09H 16-Pin ps 0800 PL123E-09HSC-R PL123E-09HSC PDF

    4606 MOSFET INVERTER

    Abstract: SMD MOSFET DRIVE DATASHEET 4606 mosfet cross reference inverter 4606 A12A 4606 inverter ic eltek flatpack LED DRIVER ana 618 uc3843 inverter circuit 4606 inverter KA3843
    Text: Shortform Catalog February 2001 http://www.micrel.com/ Micrel Semiconductor • 1849 Fortune Drive • San Jose, CA 95131 • USA • +1 408 944-0800 • +1 408 944-0970 Micrel Shortform Catalog February 2001 2001 Micrel, Inc. The information furnished by Micrel, Inc., in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use, nor any


    Original     		PDF

    J0101

    Abstract: 3233G ac104z
    Text: PRELIMINARY DATA SHEET • AC104Z Ultra Low Power 10/100 Quad SMII/RII Ethernet Transceiver GENERAL DESCRIPTION FEATURES The AC104Z is a highly integrated, 3.3V, low-power, fourport, 10BASE-T/100BASE-TX, Ethernet transceiver implemented in 0.35µm CMOS technology. Multiple modes of


    Original     		AC104Z AC104Z 10BASE-T/100BASE-TX, 100FX 128PQFP AC104Z-DS01-R J0101 3233G PDF

    AC104ZKQM

    Abstract: block diagram of broadcom 3233G ac104z
    Text: PRELIMINARY DATA SHEET • AC104Z Ultra Low Power 10/100 Quad SMII/RMII Ethernet Transceiver G E NE R AL D E SC R IPT IO N FEATURES The AC104Z is a highly integrated, 3.3V, low-power, fourport, 10BASE-T/100BASE-TX, Ethernet transceiver implemented in 0.35µm CMOS technology. Multiple modes of


    Original     		AC104Z AC104Z 10BASE-T/100BASE-TX, 100FX 128PQFP AC104Z-DS02-R AC104ZKQM block diagram of broadcom 3233G PDF

    TSOP-48 pcb LAYOUT

    Abstract: str 6654 pin details of str f 6654 pin details of str W 6654 amd socket 940 pinout str W 6654 land pattern tsop 66 56-Lead TSOP Package 28F002BC 28F010
    Text: D Small Outline Package Guide 1996 296514-006 8/19/97 5:26 PM FRONT.DOC Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions


    Original     		PDF

    PAL 007 pioneer

    Abstract: pioneer PAL 007 A PAL 008 pioneer sn 7600 n 648-0482211 sem 2106 Trays tsop56 TSOP 86 land pattern amd socket 940 pinout Meritec 980020-56
    Text: D Small Outline Package Guide 1999 3/25/99 4:28 PM cvrpg.doc Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions


    Original     		PDF

    pioneer PAL 007 A

    Abstract: PAL 007 pioneer str 6654 PAL 008 pioneer pin details of str W 6654 sem 2106 Yamaichi Electronics ic197 648-0482211 TSOP56 jackson
    Text: D Small Outline Package Guide 1999 3/25/99 4:28 PM cvrpg.doc Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions


    Original     		PDF

    land pattern for TSOP 2-44

    Abstract: Wells programming adapter TSOP 48 intel 44-lead psop land pattern for TSOP 56 pin F9232 E28F016SA70 tsop tray matrix outline wells 648-0482211 memory card thickness 29f200 tsop adapter
    Text: D Small Outline Package Guide 1996 296514-006 8/19/97 5:26 PM FRONT.DOC Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions


    Original     		PDF

    WLCSP smt

    Abstract: EIA-481-D-2008 Cu OSP and Cu SOP qfn tray pocket size 5 x 6 SUF1577-15 WLCSP stencil design without underfill SAC396 cte table flip chip substrate SAC 2.3 Ag bump composition
    Text: AN69061 Design, Manufacturing, and Handling Guidelines for Cypress Wafer-Level Chip Scale Packages WLCSP Author: Wynces Silvoza, Bo Chang Associated Project: No Associated Part Family: All Cypress WLCSP products Software Version: None Associated Application Notes: None


    Original     		AN69061 AN69061 WLCSP smt EIA-481-D-2008 Cu OSP and Cu SOP qfn tray pocket size 5 x 6 SUF1577-15 WLCSP stencil design without underfill SAC396 cte table flip chip substrate SAC 2.3 Ag bump composition PDF

    ft232rc

    Abstract: No abstract text available
    Text: Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.11 Clearance No.: FTDI# 38 Future Technology Devices International Ltd. FT232R USB UART IC The FT232R is a USB to serial UART interface with the following advanced features: • FIFO receive and transmit buffers for high data


    Original     		FT232R ft232rc PDF

    AC101LKQT

    Abstract: AC101L AC101L circuit crs 600 A1297
    Text: PRELIMINARY DATA SHEET • AC101L Ultra Low Power 10/100 Ethernet Transceiver with Auto_MDIX DESCRIPTION F E AT U R E S The AC101L is a single channel, low power, 10/100BASE-TX/FX Transceiver. The AC101L has an integrated voltage regulator to allow operation from a


    Original     		AC101L AC101L 10/100BASE-TX/FX 10BASE-T/100BASE-TX/100BASE-FX AC101L-DS01-RDC AC101LKQT AC101L circuit crs 600 A1297 PDF

    PPM5

    Abstract: No abstract text available
    Text: PM8353 QuadPHY Datasheet Preliminary PM8353 QUADPHYTM 4 CHANNEL PHYSICAL LAYER TRANSCEIVER WITH GIGABIT ETHERNET PCS AND TRUNKING 1.0 TO 1.25 GBPS INTERFACES DATASHEET DOCUMENT ISSUE 6 ISSUED MARCH, 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE


    Original     		PM8353 PM8353 PMC-2000650, PMC-2000651, PMC-2000651 PPM5 PDF

    ZF40

    Abstract: PM8351
    Text: PM8351 OctalPHY Datasheet Preliminary PM8351 OCTALPHYTM 8 CHANNEL PHYSICAL LAYER TRANSCEIVER WITH GIGABIT ETHERNET PCS AND TRUNKING FOR 1.0 TO 1.25 GBPS INTERFACES DATA SHEET DOCUMENT ISSUE 6 ISSUED MARCH 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE


    Original     		PM8351 PM8351 PMC-2000650, PM8353 PMC-2001193 PMC-2000650 3u-1995 ZF40 PDF