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    Abstract: No abstract text available
    Text: QL3060 / QL3060R 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density PRELIMINARY DATA . 60,000 usable PLD gates, 316 I/O pins S High Performance and High Density -60,000 Usable PLD Gates with 316 I/Os -16-bit counter speeds over 250 MHz, data path speeds over 275 MHz


    OCR Scan     		PDF QL3060 QL3060R -16-bit