LU120N
Abstract: hm658128lp HM658128 HM658128LFP-10 LR 120N
Text: HITACHI/ LOGIC/ARRAYS/NEM 31E P • 441L203 OOlbba'I b ■ HM658128 Series- r-HU'23-25 131072-word x 8-bit High Speed CMOS Pseudo Static RAM The Hitachi HM658128 is a pseudo-static RAM organized as 131,072-word x 8-bit. HM658128 realizes low power consump
|
OCR Scan
|
PDF
|
HM65812S
131072-word
HM658128
072-word
256k-bit
100/120/150ns
HN27C4096
LU120N
hm658128lp
HM658128LFP-10
LR 120N
|
Untitled
Abstract: No abstract text available
Text: 5QE D 44^503 G01341Q 5 HITACHI/ L0GIC/ARRAYS/MÉÎ1 0 H IT A C H I S e p t e m b e r , 1985 CMOS GATE ARRAYS i HD61 SERIES DESIGNER'S MANUAL AND PRODUCT SPECIFICATION HITACHI/ LOGIC/ARR'A YS/MEM SQE D • 4 4TLS03 0G13411 4 T -42-11-09 CMOS GATE ARRAYS HD61 SERIES
|
OCR Scan
|
PDF
|
G01341Q
4TLS03
0G13411
HD14070B
1407IB
HD14556B
HD14558B
HD14560B
HD14562B
HD14072B
|
Untitled
Abstract: No abstract text available
Text: HM5216326 Serie 16M LVTTL interface SGRAM 2-Mword x 32-bit 125 MHz/100 MHz/83 MHz HITACHI ADE-203-678B (Z) Preliminary, Rev. 0.3 Jan. 14,1998 Description All inputs and outputs signals refers to the rising edge of the clock input. The HM5216326 provides 2
|
OCR Scan
|
PDF
|
HM5216326
32-bit)
Hz/100
Hz/83
ADE-203-678B
FP-100H
TFP-100H
|
Untitled
Abstract: No abstract text available
Text: HM51W18165I Series 1 0 4 8 5 7 6 -w o rd x 1 6 - b it D y n a m ic R A M HITACHI A D E -2 0 3 -7 5 5 A Z R e v . 1.0 M a r. 1 0 ,1 9 9 7 Description The Hitachi HM51W18165I is a CMOS dynamic RAM organized as 1,048,576-word x 16-bit. It employs the most advanced CMOS technology for high performanceand low power. The HM51W18165I offers
|
OCR Scan
|
PDF
|
HM51W18165I
576-word
16-bit.
42-pin
ns/70
441b203
DG332Ã
|
Untitled
Abstract: No abstract text available
Text: HITACHI/ LOGIC/ARRAYS/N b7E D • 44^203 0024374 HM514800A/AL, HM51S4800A/AL Series 7 b cl ■ HITE Preliminary 524,286-Word x 8-Bit Dynamic Random Access Memory ■ DESCRIPTION ■ FEATURES The Hitachi HM514800A are CMOS dynamic RAM orga nized as 524,288-word x 8-bit. HM514800A have realized
|
OCR Scan
|
PDF
|
HM514800A/AL,
HM51S4800A/AL
286-Word
HM514800A
288-word
28-pin
|
mvab
Abstract: ZW22 HM5241605 HM5241605TT-15 HM5241605TT-17 HM5241605TT-20
Text: ADE-203-186A Z HM5241605 Series 131,072-word x 16-bit x 2-bank Synchronous Dynamic RAM A ll inputs and outputs are referred to the rising edge o f the clock input. The HM5241605 is offered in 2 banks for improved performance. Features Ordering Information
|
OCR Scan
|
PDF
|
ADE-203-186A
HM5241605
072-word
16-bit
Hz/57
Hz/50
P////77K
///7//77//7/7X
mvab
ZW22
HM5241605TT-15
HM5241605TT-17
HM5241605TT-20
|
memory cats
Abstract: HM5118160B HM5118160BJ-6 HM5118160BJ-7 HM5118160BJ-8 HM5118160BLJ-6 HM5118160BLJ-7 HM5118160BLJ-8
Text: HM5118160B Series 1048576-word x 16-bit Dynamic Random Access Memory HITACHI ADE-203-476 Z Preliminary Rev. 0.0 Dec. 6, 1995 Description The Hitachi HM5118160B is a CMOS dynamic RAM organized as 1,048,576-word x 16-bit. It employs the most advanced CMOS technology for high performance and low power. The HM5118160B offers Fast Page
|
OCR Scan
|
PDF
|
HM5118160B
1048576-word
16-bit
ADE-203-476
576-word
16-bit.
ns/70
ns/80
memory cats
HM5118160BJ-6
HM5118160BJ-7
HM5118160BJ-8
HM5118160BLJ-6
HM5118160BLJ-7
HM5118160BLJ-8
|
Untitled
Abstract: No abstract text available
Text: HB526A264DB Series 1,048,576-word x 64-bit x 2-bank Synchronous Dynamic RAM Module HITACHI ADE-203-607 Z Preliminary Rev. 0.1 May. 20,1997 Description The HB526A264DB is a lM x 64 x 2 banks Synchronous Dynamic RAM Small Outline Dual In-line Memory Module (S.O.DIMM), mounted 8 pieces of 16-Mbit SDRAM (HM5216805TT/HM5216805LTT)
|
OCR Scan
|
PDF
|
HB526A264DB
576-word
64-bit
ADE-203-607
16-Mbit
HM5216805TT/HM5216805LTT)
24C02)
144-pin
|
HM514800CLZ7
Abstract: No abstract text available
Text: HM51 S 4800A/AL Series HM51(S)4800C/CL Series 524,288-word x 8-bit Dynamic Random Access Memory The Hitachi HM514800A/AL, HM514800C/CL are CMOS dynamic RAM organized as 524,288word x 8-bit HM514800A/AL, HM514800C/CL have realized higher density, higher perfonnance
|
OCR Scan
|
PDF
|
800A/AL
4800C/CL
288-word
HM514800A/AL,
HM514800C/CL
288word
HM514800C/CL
HM514800CLZ7
|
Untitled
Abstract: No abstract text available
Text: HM5221605 Series Prelim inary 65,536-word x 16-bit x 2-bank Synchronous Dynamic RAM A ll inputs and outputs are referred to the rising edge o f the clock input. The HM5221605 is offered in 2 banks for improved performance. Features Ordering Information Type No.
|
OCR Scan
|
PDF
|
HM5221605
536-word
16-bit
HM5221605TT-20
HM5221605TT-17
HM522160517-15
400-mil
50-pin
TTP-50DA)
|