ALi M6759 A1
Abstract: ALI M6759 M6759 A1 ACER LABORATORIES INC M6759 7474 pin out diagram 7474 ic pin configuration 8052 basic external DIAGRAM OF IC 7474 80C51
Text: Acer Laboratories Inc. M6759: 8 bit MTP Micro-controller -Proprietary, Confidential, Preliminary- Product Brief M6759 : 8 Bit MTP Micro-controller Features l l l l l l l l l l l l l l 8051 instruction set compatible 8 bit microcontroller 8051/8052 compatible pin out
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M6759:
M6759
o852-2730
1830-B
6759DS02
ALi M6759 A1
ALI M6759
M6759 A1
ACER LABORATORIES INC
M6759
7474 pin out diagram
7474 ic pin configuration
8052 basic
external DIAGRAM OF IC 7474
80C51
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8052 basic
Abstract: 7474 pin out diagram ALI M6759 M6759 A1 ALi M6759 A1 7474 pin configuration 7474 pin diagram features of ic 7474 INTERNAL DIAGRAM OF IC 7474 8052 pin structure
Text: Acer Laboratories Inc. M6759: 8 bit MTP Micro-controller -Proprietary, Confidential, Preliminary- Product Brief M6759 : 8 Bit MTP Micro-controller Features 8051 instruction set compatible 8 bit microcontroller 8051/8052 compatible pin out Complete static design, wide range of
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M6759:
M6759
s852-2730
1830-B
6759DS02
8052 basic
7474 pin out diagram
ALI M6759
M6759 A1
ALi M6759 A1
7474 pin configuration
7474 pin diagram
features of ic 7474
INTERNAL DIAGRAM OF IC 7474
8052 pin structure
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1352B
Abstract: AT91SAM7XC128 AT91SAM7XC256 AT91SAM7XC512 ISO7816 digital object counter aes 128 algorithm object code
Text: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support
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32-bit
16-bit
AT91SAM7XC512)
AT91SAM7XC256)
AT91SAM7XC128)
6209DS
17-Feb-09
1352B
AT91SAM7XC128
AT91SAM7XC256
AT91SAM7XC512
ISO7816
digital object counter
aes 128 algorithm object code
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AT91SAM7XC256B-AU
Abstract: atmel 0740 AT91SAM7XC128 AT91SAM7XC256 AT91SAM7XC512 ISO7816 atmel 841 aes 128 algorithm object code
Text: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support
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32-bit
16-bit
AT91SAM7XC512)
AT91SAM7XC256)
AT91SAM7XC128)
6209DS
17-Feb-09
AT91SAM7XC256B-AU
atmel 0740
AT91SAM7XC128
AT91SAM7XC256
AT91SAM7XC512
ISO7816
atmel 841
aes 128 algorithm object code
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Untitled
Abstract: No abstract text available
Text: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support
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32-bit
16-bit
AT91SAM7XC512)
AT91SAM7XC256)
AT91SAM7XC128)
6209DSâ
17-Feb-09
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iso7816 sim
Abstract: detector brownout ISO7816 AT91SAM7XC128 AT91SAM7XC256 AT91SAM7XC512 ETXCK-ERXCK
Text: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support
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32-bit
16-bit
AT91SAM7XC512)
AT91SAM7XC256)
AT91SAM7XC128)
6209CS
08-Dec-08
iso7816 sim
detector brownout
ISO7816
AT91SAM7XC128
AT91SAM7XC256
AT91SAM7XC512
ETXCK-ERXCK
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AT91SAM7XC128
Abstract: AT91SAM7XC256 AT91SAM7XC512 ISO7816 aes 128 algorithm object code
Text: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support
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Original
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PDF
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32-bit
16-bit
AT91SAM7XC512)
AT91SAM7XC256)
AT91SAM7XC128)
6209DS
17-Feb-09
AT91SAM7XC128
AT91SAM7XC256
AT91SAM7XC512
ISO7816
aes 128 algorithm object code
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STM8S903
Abstract: 903K3 5401 DM stm8s903k STM8 S 903 K 3 T 6 C TR pm0051 UM04 ic 8038 STM8 CPU programming manual switching regulator ic LM 5304
Text: STM8S903K3 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, 1 Kbyte RAM, 640 bytes EEPROM,10-bit ADC, 2 timers, UART, SPI, I²C Preliminary data Features Core • ■ 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline LQFP32 7x7 VFQFPN32 5x5
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STM8S903K3
10-bit
LQFP32
VFQFPN32
16-bit
STM8S903
903K3
5401 DM
stm8s903k
STM8 S 903 K 3 T 6 C TR
pm0051
UM04
ic 8038
STM8 CPU programming manual
switching regulator ic LM 5304
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SSD2119
Abstract: Resolution ta 9690 gn SSD2119Z7 SSD2119 application note S945 up 6103 s8 equivalent pin diagram of ic 7489 s937 sj 8227
Text: SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD2119 Advance Information 320 RGB x 240 TFT LCD Driver Integrated Power Circuit, Source and Gate Driver and RAM This document contains information on a new product. Specifications and information herein are subject to change
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SSD2119
SSD2119
2002/95/EC)
SJ/T11364-2006)
Resolution
ta 9690 gn
SSD2119Z7
SSD2119 application note
S945
up 6103 s8 equivalent
pin diagram of ic 7489
s937
sj 8227
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Untitled
Abstract: No abstract text available
Text: STM8S903K3 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, 1 Kbyte RAM, 640 bytes EEPROM,10-bit ADC, 2 timers, UART, SPI, I²C Preliminary data Features Core • 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline ■ Extended instruction set
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STM8S903K3
10-bit
LQFP32
VFQFPN32
16-bit
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5257B
Abstract: No abstract text available
Text: TOSHIBA TC55257BH/BH/BSPI/BFTI/BTRI-10L SILICON GATE CMOS 32,768 WORD x 8 BIT STATIC RAM Description The T C 5 5257 B P I is a 2 6 2 ,1 4 4 bit C M O S static ra ndom acce ss m e m ory organized as 3 2 ,7 6 8 w o rd s b y 8 bits and operated from a single 5V po w e r supply. A dvanced circuit tech nique s provide bo th high speed an d low p o w e r features w ith an operating current o f
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TC55257BH/BH/BSPI/BFTI/BTRI-10L
100ns.
5257B
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tc55257
Abstract: 5257 static ram 5257
Text: TOSHIBA TC55257BPI/BFVBSPI/BFn/BTRI-10L SILICON GATE CMOS 32,768 WORD x 8 BIT STATIC RAM Description The T C 55257B P I is a 2 6 2 ,1 4 4 bit C M O S sta tic ra ndom acce ss m e m ory organized as 3 2 ,7 6 8 w o rd s b y 8 bits and operated from a single 5V p o w e r supply. A dvan ced circuit tech nique s provide bo th high speed and low p o w e r features w ith an operating current o f
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TC55257BPI/BFVBSPI/BFn/BTRI-10L
55257B
100ns.
TC55257BPI/BFI/BSPI/BFTI/BTRM
tc55257
5257 static ram
5257
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TC552570
Abstract: No abstract text available
Text: TOSHIBA TC55257CPI/CFVCSPI/CFTI/CTRI-85L/10L SILICON GATE CMOS PRELIMINARY 32,768 WORD x 8 BIT STATIC RAM Description T h e T C 5 5 2 5 7 C P I is a 2 6 2 ,1 4 4 bit C M O S static random acce ss m e m ory organized as 3 2 ,7 6 8 w o rd s by 8 bits and operated from a
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TC55257CPI/CFVCSPI/CFTI/CTRI-85L/10L
55257C
TC552570
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Untitled
Abstract: No abstract text available
Text: TOSHIBA TC55257CPL/CFL/CSPI7CFTL/CTRL-70L/85L/10L PRELIMINARY SILICON GATE CMOS 32,768 WORD x 8 BIT STATIC RAM Description The T C 5 5 2 5 7 C P L is a 26 2,14 4 bit C M O S static random a cce ss m em ory organized as 3 2 ,7 6 8 w o rd s by 8 bits and operated from
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TC55257CPL/CFL/CSPI7CFTL/CTRL-70L/85L/10L
TC55257CPL/CFL/CSPL/CFTL/CTRL-70L/85L/10L
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Untitled
Abstract: No abstract text available
Text: *10*17240 TOSHIBA 002ÔÔ0Ô IS I TC55257DPI/DFI/DFn-70L/-$5L PRELIMINARY SILICON GATE CMOS 32,768 WORD x 8 BIT STATIC RAM Description T h e T C 5 5 2 5 7 D P I is a 2 6 2 ,1 4 4 bit s ta tic ra n d o m a c c e s s m e m o ry organize d as 3 2 ,7 6 8 w o rd s b y 8 b its using C M O S te c h
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TC55257DPI/DFI/DFn-70L/-
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Untitled
Abstract: No abstract text available
Text: • b E 4 ci ñ a S G0 1 fe>5 5 O 7 ■ MITSUBISHI LSls MH25609SN-10 . M ITSU B ISH I M EMORY/ASIC ETE D 2 3 5 9 2 9 6 -B IT (2 6 2 144-WORD BY 9-BIT)CM0S STATIC RAM T * - ‘/ k ' A ì - W DESCRIPTION The M H 25609SN is a 2 3 5 6 2 9 6 -b it C M O S static R A M
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MH25609SN-10
144-WORD
25609SN
35-pin
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5m5256
Abstract: 74hc138m TL-100NS
Text: MITSUBISHI LSIs MH25609ASN-10 2359296-BIT 262144-WORD BY 9-BIT CMOS STATIC RAM DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M H 2 5 6 0 9 A S N is a 2 3 5 9 2 9 6 - b it CMOS static RAM m odule organized as 2 6 2 1 4 4 -w o rd by 9 -b its. It consists o f eight industry standard 3 2 K x 8 static RAM s, 2 5 6 K x 1
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MH25609ASN-10
2359296-BIT
262144-WORD
5m5256
74hc138m
TL-100NS
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Untitled
Abstract: No abstract text available
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM40100 1M x 40 Bit Dynamic Random Access Memory Module for Error Correction Applications The M C M 40100 is a 40M dynam ic random a ccess m em ory D RAM m odules o rganized as 1,048,576 x 4 0 bits. The m odule is a 72-lead single-in-line m em ory
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MCM40100
72-lead
54400AN
4400A
40100AS60
40100AS70
40100ASG
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Untitled
Abstract: No abstract text available
Text: Am2932 Am2932 Program Control Unit/Push-Pop Stack DISTINCTIVE CHARACTERISTICS Powerful, 4-bit sNce address controller for memories Eight relative address instructions Useful with both main memory and microprogram mem ory Expandable to generate any address length
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Am2932
400mA
Am2902A
Am2904
Am2920
Am2922
03641B
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82395DX
Abstract: cr 5228 t intel 82395 82395 DMLF 164 weitek sd21, phi intel 82385 29038 weitek 3171
Text: in te i 82395DX HIGH PERFORMANCE SMART CACHE Optimized intel386TM DX Microprocessor Companion Concurrent Line Buffer Cacheing Integrated 16KB Data RAM Expandable - up to 64KB Supports lntel486TM Microprocessor like Burst Multiprocessor Support 4 Way SET Associative with Pseudo
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82395DX
intel386TM
lntel387
lntel486TM
33MHz
32-Bit
cr 5228 t
intel 82395
82395
DMLF 164
weitek
sd21, phi
intel 82385
29038
weitek 3171
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lifo stack
Abstract: 6939C
Text: zeezuiv Am2932 Program Control Unit/Push-Pop Stack DISTINCTIVE CHARACTERISTICS Powerful, 4-blt slice address controller for memories Useful with both main memory and microprogram mem ory Expandable to generate any address length Executes 16 instructions
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Am2932
Am2932
Am2902A
Am2904
Am2920
Am2922
lifo stack
6939C
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lifo stack
Abstract: pin diagram of full adder using Multiplexer IC pinout AM2 AMD D-20 20-PIN CERDIP 4560d
Text: Am2932 Am 2932 Program Control Unit/Push-Pop Stack DISTINCTIVE CHARACTERISTICS Eight relative address instructions Including Jum p relative and Jum p-to-Subroutine rela tive S eventeen-level pu sh /po p stack On-chip storage o f subroutine return addresses
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Am2932
Am2902A
Am2904
Am2920
Am2922
03641B
lifo stack
pin diagram of full adder using Multiplexer IC
pinout AM2 AMD
D-20
20-PIN CERDIP
4560d
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54400AN
Abstract: No abstract text available
Text: i v iv s i v n v u n • SEMICONDUCTOR TECHNICAL DATA MCM40200 MCM40L200 2M x 40 Bit Dynamic Random Access Memory Module for Error Correction Applications The M CM 40200 and M C M 40L200 are 80M dynam ic random access m em ory DRAM m odules organized as 2,097,152 x 40 bits. The module is a double-sided
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40L200
72-lead
54400AN
MCM40200
MCM40L200
MOTOD010
4QL200
MCM40200AS60
MCM40200AS70
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rs307
Abstract: No abstract text available
Text: BENCHMARQ_ bq4852Y RTC Module With 512Kx8 NVSRAM Features General Description >• I n t e g r a t e d SR A M , r e a l - t i m e clock, C PU su p erv iso r, c ry sta l, p o w er-fail c o n tro l c irc u it, a n d b attery The bq4852Y RTC Module is a non
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bq4852Y
512Kx8
10-year
304-bit
rs307
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