68HC708KL8
Abstract: CPU08 HC05 M146805 M6805 M68HC05 M68HC08 Nippon capacitors
Text: HC708KL8GRS/D REV. 1.0 68HC708KL8 General Release Specification July 14, 1997 CSIC Consumer and Smartcard Microcontroller Division Austin, Texas N O N - D I S C L O S U R E A G R E E M E N T R E Q U I R E D General Release Specification Motorola reserves the right to make changes without further notice to
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HC708KL8GRS/D
68HC708KL8
68HC708KL8
CPU08
HC05
M146805
M6805
M68HC05
M68HC08
Nippon capacitors
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C4558
Abstract: C4554 C4557 c455 CY7C455-14JI CY7C455 CY7C456 CY7C457 CY7C447
Text: CY7C455 CY7C456 CY7C457 512 x 18, 1K x 18, and 2K x 18 Cascadable Clocked FIFOs with Programmable Flags • Depth Expansion Capability • 52-pin PLCC and 52-pin PQFP Features • High-speed, low-power, first-in first-out FIFO memories • 512 x 18 (CY7C455)
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CY7C455
CY7C456
CY7C457
52-pin
CY7C455)
CY7C456)
CY7C457)
83-MHz
C4558
C4554
C4557
c455
CY7C455-14JI
CY7C455
CY7C456
CY7C457
CY7C447
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upsd
Abstract: UPS3200 TQFP52 TQFP80 uPSD3200 uPSD3233B uPSD3233BV uPSD3234A uPSD3234A-40 uPSD3234BV
Text: uPSD3234A, uPSD3234BV uPSD3233B, uPSD3233BV Flash Programmable System Devices with 8032 Microcontroller Core FEATURES SUMMARY • The uPSD323X Devices combine a Flash PSD architecture with an 8032 microcontroller core. The uPSD323X Devices of Flash PSDs feature dual banks of Flash memory, SRAM,
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uPSD3234A
uPSD3234BV
uPSD3233B
uPSD3233BV
uPSD323X
16-bit
128change
upsd
UPS3200
TQFP52
TQFP80
uPSD3200
uPSD3234A-40
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23TI
Abstract: UPS3200 TQFP52 TQFP80 uPSD3253B uPSD3253BV uPSD3254A uPSD3254BV uPSD325X BV-24
Text: uPSD3254A, uPSD3254BV uPSD3253B, uPSD3253BV Flash Programmable System Devices with 8032 Microcontroller Core FEATURES SUMMARY • The uPSD325X devices combine a Flash PSD architecture with an 8032 microcontroller core. The uPSD325X devices of Flash PSDs feature dual banks of Flash memory, SRAM,
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uPSD3254A
uPSD3254BV
uPSD3253B
uPSD3253BV
uPSD325X
16-bit
32KByte
128KBychange
23TI
UPS3200
TQFP52
TQFP80
BV-24
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8T33FS6221
Abstract: No abstract text available
Text: DATA SHEET MC100ES6221 Freescale Semiconductor Technical Data Rev 5, 04/2005 Low Voltage 1:20 Differential ECL/PECL/HSTL Clock LowBuffer Voltage 1:20 Differential Fanout MC100ES6221 MC100ES6221 ECL/PECL/HSTL Clock Buffer PRODUCT DISCONTINUATION NOTICEFanout
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MC100ES6221
MC100ES6221
199707558G
8T33FS6221
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W2L14Z225M
Abstract: LLA219C70G225M LTC5569 LTC2271 LTC5584 LTC5585
Text: LTC2271 16-Bit, 20Msps Serial Low Noise Dual ADC FEATURES DESCRIPTION n The LTC 2271 is a 2-channel, simultaneous sampling 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that
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LTC2271
16-Bit,
20Msps
16-bit
44LSBRMS.
siV/600mW,
530MHz,
31dBm
80dBm,
W2L14Z225M
LLA219C70G225M
LTC5569
LTC5584
LTC5585
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atmel 80C52X2
Abstract: 80C52X2 AT89C5131A-RD at89c5131 parallel programmer AT89C5131 PLCC 52 AT89C5131 80C51 80C52 AT89C5131A-L PLCC52
Text: Features • 80C52X2 Core 6 Clocks per Instruction • • • • • • • • • • • • • • • • • • • – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enhanced UART (EUART) – Three 16-bit Timer/Counters: T0, T1 and T2
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80C52X2
16-bit
16/32-Kbyte
4338E
atmel 80C52X2
AT89C5131A-RD
at89c5131 parallel programmer
AT89C5131 PLCC 52
AT89C5131
80C51
80C52
AT89C5131A-L
PLCC52
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LVEP221
Abstract: NB100LVEP221 NB100LVEP221FA NB100LVEP221FAR2
Text: NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver The NB100LVEP221 is a low skew 1-to-20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential
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NB100LVEP221
NB100LVEP221
1-to-20
LVEP221
r14525
NB100LVEP221/D
NB100LVEP221FA
NB100LVEP221FAR2
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AN1545
Abstract: MPC961C MPC991 analog vco
Text: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview 3.3V Differential ECL/PECL Order Number: MPC9991/D Rev 0, 12/2001 MPC9991 PLL Clock Generator The MPC9991 is a 3.3 V compatible, PLL based ECL/PECL clock driver. Using SiGe technology and a fully differential design ensures
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MPC9991/D
MPC9991
MPC9991
AN1545
MPC961C
MPC991
analog vco
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AD1839A
Abstract: AD1839AAS AD1839AAS-REEL OP275 TDM256
Text: a 2 ADC, 8 DAC, 96 kHz, 24-Bit ⌺-⌬ Codecs AD1839A FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Interface Supports up to 96 kHz Sample Rates 192 kHz Sample Rate Available on 1 DAC Supports 16-/20-/24-Bit Word Lengths Multibit ⌺-⌬ Modulators with
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24-Bit
AD1839A
16-/20-/24-Bit
OP275
560pF
150pF
52-Lead
MO-022-AC
C03627
AD1839A
AD1839AAS
AD1839AAS-REEL
OP275
TDM256
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LVE222
Abstract: MC100LVE222 MC100LVE222FA MC100LVE222FAR2 MB113
Text: MC100LVE222 3.3 V ECL 1:15 Differential ÷1/÷2 Clock Driver The MC100LVE222 is a low skew 1:15 differential ÷1/÷2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single- ended with VBB output reference bypassed and connected to the
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MC100LVE222
MC100LVE222
LVE222
r14525
MC100LVE222/D
MC100LVE222FA
MC100LVE222FAR2
MB113
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USR24
Abstract: ssi protocol 73D2248
Text: SSI 73D2248/2348 & MNP5, V.42bis Datacom Modem Device Set i k m M s l m s ' A TDK Group/Company Advance Information January 1993 FEATURES DESCRIPTION The SSI 73D2248/2348 Chip Sets consists of two CMOS integrated circuits which provide the data pump and protocol functions required to implement a high
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73D2248/2348
42bis
73D2248/2348
73D2248
73K224L
22bis
73D246
USR24
ssi protocol
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OR73
Abstract: 73k312l 73K222
Text: 0253^5 ÜDDTflTG MOb « S I L SSI 73K312L Bell 202,103 and CCITT V.23, V.21 Single-Chip Modem A TDK Group/Company Preliminary Data SILI CO N SYSTEMS INC DESCRIPTION L IE D December 1992 ~ 7S -3 Z -Ú > 5 FEATURES Bell 202, 103 and CCITT V.23, V.21 slngle-chlp
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73K312L
73K312L
1292-rev.
OR73
73K222
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32F8020
Abstract: No abstract text available
Text: ju t 1 « * » SSI 32P4722 jilic o n á tík m í' Pulse Detector & Data Separator A TDK Group/Company Advance Information June 1993 DESCRIPTION FEATURES The SSI 32P4722 is a low power, high performance bipolar device that provides pulse detection, data synchronization, and ENDEC electronics on a single
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32P4722
32P4722
extern52-Pin
32F8020
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SPT5230
Abstract: SPT5230SCT 1022 load cell
Text: @ S P SPT5330 T 10-BIT, 36 MWPS TRIPLE VIDEO DAC SIGNAL PROCESSING TECHNOLOGIES APPLICATIONS FEATURES Desktop Video Processing CCIR-601 Video Signal Processing RGB Color Monitors Image Processing Direct Digital Synthesis 10-Bit Triple Video Digital-to-Analog Converter
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SPT5230
10-BIT,
10-Bit
52-pin
CCIR-601
SPT5230
controls30SCT
G0D3337
SPT5230SCT
1022 load cell
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UT AT66
Abstract: No abstract text available
Text: DEVICE SPECIFICATION 20-OUTPUT CLOCK DRIVER FEATURES • 20 clock outputs: - Ten outputs at primary frequency, up to 80 MHz - Ten outputs at primary or 1/2 primary frequency, in two groups of five outputs • Leading edge skew for all outputs <0.5 ns • Proprietary output drivers with:
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20-OUTPUT
SC3507
84-unit
52-pin
SC3507Q-1/D
UT AT66
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Untitled
Abstract: No abstract text available
Text: DEVICE SPECIFICATION 20-O U TPU T LVTTL C LO C K DRIVER FEATURES • 20 clock outputs at primary frequency up to 100 MHz • All outputs are leading edge synchronized to within <0.5 ns • Proprietary output drivers with: - Complementary 24 mA peak outputs, source
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S3LV308
84-unit
52-pin
S3LV308Q-1/D
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G530T
Abstract: No abstract text available
Text: •HYUNDAI H Y 6 7 1 6 1 1 0 / 1 Ì 1 64K X 16 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64Kx16 SRAM core, address registers, data input registers, a 2-bit burst address counter and Non-pipelined output. All synchronous inputs pass through registers controlled by a
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64Kx16
486/Pentium
15ns/20ns/25ns
67MHz
Mb75Qflfl
GG0b313
10H07-11-MAY95
HY6716110/111
4b750flfl
1DH07-11-MAY95
G530T
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Untitled
Abstract: No abstract text available
Text: •HYUNDAI H Y 6 7 V 1 8 1 0 0 /1 0 1 64K X 18 Bit SYNCHRONOUS CMOS SRAM PRELIMINARY DESCRIPTION This device integrates high-speed 64K x18 SRAM core, address registers, data input registers, a 2-bit burst ad dress counter and pipelined output. All synchronous inputs pass through registers controlled by a positiveedge triggered clock K .
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486/Pentium
7ns/12ns/17ns
67MHz
486/Pent
00DbSS3
1DH02-22-MAY95
HY67V18100/101
HY67V18100C
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cy7c131-55nc
Abstract: ZT12 CY7C130 CY7C131 CY7C140 CY7C141 IDT7130 IDT7140
Text: CY7C130/CY7C131 CY7C140/CY7C141 W CYPRESS Features • 0.8-micron CMOS for optimum speed/power • Automatic power-down • TTL compatible • Capable o f withstanding greater than 2001V electrostatic discharge • Fully asynchronous operation • Master CY7C130/CY7C131 easily ex
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CY7C130/CY7C131
CY7C140/CY7C141
CY7C140/
CY7C141
CY7C130/
CY7C131;
IDT7130
IDT7140
cy7c131-55nc
ZT12
CY7C130
CY7C131
CY7C140
CY7C141
IDT7140
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adsh 13
Abstract: intel 80486 CY7C1031 CY7C1032 VXXXX
Text: CY7C1031 CY7C1032 PRELIMINARY ?CYPRESS Functional Description continued Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) is LOW and (2) AD5P is LOW. ADSP-triggered write cycles are completed in two clock periods. The address at Ao
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CY7C1031
CY7C1032
CY7C1031
CY7C1032will
52-Lead
CY7C1032-
CY7C1032â
CY7C1032-8NC
adsh 13
intel 80486
CY7C1032
VXXXX
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ZE 004
Abstract: SPT5230 SPT5230SCT 1022 load cell ir3d
Text: SPTS230 @ S PT 10-BIT, 36 MWPS TRIPLE VIDEO DAC S/GNAL PROCESSING TECHNOLOGIES FEATURES APPLICATIONS Desktop Video Processing CCIFt-601 Video Signal Processing RGB Color Monitors Image Processing Direct Digital Synthesis 10-Bit Triple Video Digital-to-Analog Converter
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10-BIT,
10-Bit
52-pin
CCIR-601
SPT5230
SPT5230
ZE 004
SPT5230SCT
1022 load cell
ir3d
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PDF
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1E76
Abstract: 00FF M68HC05 65r5 S002D non-user mode
Text: Order this document by MC68HC05M4TS/D REV. 1 MOTOROLA SEMICONDUCTOR m m TECHNICAL DATA MC68HC05M4 Technical Summary 8-Bit Microcontroller Unit The MC68HC05M4 HCMOS microcontroller unit MCU is a member of the M68HC05 Family of microcontrollers. This high-performance, low-power MCU has parallel I/O capability with pins programmable as input or output. Addi
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MC68HC05M4
M68HC05
1ATX31587-0
MC68HC05M4TS/D
MC68HC05M4TS/D
1E76
00FF
65r5
S002D
non-user mode
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY '# CYPRESS 32Kx 18 Synchronous Cache RAM Features • Direct interface with the processor and external cache controller • Supports 66-MHz Pentium micro processor cache systems with zero wait states • Asynchronous output enable • I/Os capable o f 3.3V operation
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66-MHz
CY7C178)
CY7C179)
CY7C178
CY7C179
52-pin
CY7C179â
52-Lead
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