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    54 DUAL JK FAIRCHILD Search Results

    54 DUAL JK FAIRCHILD Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    FO-DUALSTLC00-001 Amphenol Cables on Demand Amphenol FO-DUALSTLC00-001 ST-LC Duplex Multimode 62.5/125 Fiber Optic Patch Cable (OFNR Riser) - 2 x ST Male to 2 x LC Male 1m Datasheet
    FO-DUALSTLC00-004 Amphenol Cables on Demand Amphenol FO-DUALSTLC00-004 ST-LC Duplex Multimode 62.5/125 Fiber Optic Patch Cable (OFNR Riser) - 2 x ST Male to 2 x LC Male 4m Datasheet
    FO-LSDUALSCSM-003 Amphenol Cables on Demand Amphenol FO-LSDUALSCSM-003 SC-SC Duplex Single-Mode 9/125 Fiber Optic Patch Cable (OFN-LS Low Smoke) - 2 x SC Male to 2 x SC Male 3m Datasheet
    FO-DUALLCX2MM-001 Amphenol Cables on Demand Amphenol FO-DUALLCX2MM-001 LC-LC Duplex Multimode 62.5/125 Fiber Optic Patch Cable (OFNR Riser) - 2 x LC Male to 2 x LC Male 1m Datasheet
    FO-DUALLCX2MM-003 Amphenol Cables on Demand Amphenol FO-DUALLCX2MM-003 LC-LC Duplex Multimode 62.5/125 Fiber Optic Patch Cable (OFNR Riser) - 2 x LC Male to 2 x LC Male 3m Datasheet

    54 DUAL JK FAIRCHILD Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    mm74c922

    Abstract: nte CROSS-REFERENCE SJ 76 A DIODE EMI Quad 2 input nand gate cd 4093 7400 functional cross-reference HST 4047 pinout information of CMOS 4001, 4011, 4070 32-Bit Parallel-IN Serial-OUT Shift Register Fairchild Semiconductor Integrated Circuit Data Catalog 1970 application MM74C926
    Text: Logic Product Catalog Analog Discrete Interface & Logic Optoelectronics July 2002 Across the board. Around the world. Logic Literature Table of Contents Description Literature # Advanced Logic Products Databook CROSSVOLT , Fairchild Switch, TinyLogic™, VHC


    Original     		Power247TM, mm74c922 nte CROSS-REFERENCE SJ 76 A DIODE EMI Quad 2 input nand gate cd 4093 7400 functional cross-reference HST 4047 pinout information of CMOS 4001, 4011, 4070 32-Bit Parallel-IN Serial-OUT Shift Register Fairchild Semiconductor Integrated Circuit Data Catalog 1970 application MM74C926 PDF

    74S112

    Abstract: 54 dual JK fairchild
    Text: Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and


    Original     		DM74S112 29-JUL-00) ////roarer/root/data13/imaging/BIT. 04/08032000/FAIR/08022000/DM74S112 DM74S112N DM74S112N DM74S112CW 74S112 54 dual JK fairchild PDF

    DM74ALS

    Abstract: DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A DM74ALS109
    Text: DM74ALS109A Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear General Description Features The DM54ALS109A is a dual edge-triggered flip-flop. Each flip-flop has individual J, K, clock, clear and preset inputs, and also complementary Q and Q outputs.


    Original     		DM74ALS109A DM54ALS109A DM74ALS DM74ALS109A DM74ALS109AM DM74ALS109AN LS109 M16A N16A DM74ALS109 PDF

    DM5473J

    Abstract: DM5473W DM7473N 5473FMQB 5473DMQB DM7473 J14A N14A W14B
    Text: DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock


    Original     		DM7473 DM5473J DM5473W DM7473N 5473FMQB 5473DMQB DM7473 J14A N14A W14B PDF

    ACT109

    Abstract: ACT74
    Text: AC109 • ACT109 54AC/74AC109 • 54 ACT/74 ACT 109 Dual JK Positive Edge-Triggered Flip-Flop Description Connection Diagrams The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flipflops. The clocking operation is independent of


    OCR Scan     		AC109 ACT109 54AC/74AC109 ACT/74 ACT74 ACT109 54/74AC/ACT PDF

    IC 7476

    Abstract: 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476
    Text: FAIRCHILD TTL/SSI . 9N76/5476, 7476 D UA L JK M A STER /SLA VE F LIP -F LO P W ITH SEPARATE PRESETS, CLEARS A N D CLOCKS DESCRIPTION — The T TL/S SI 9N 76 /54 7 6 , 7476 is a Dual JK Master/Slave flip-flop with separate presets, separate clears and separate clocks.


    OCR Scan     		9N76/5476, 11N76/7476 400ft IC 7476 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 7476 Connection diagram 7476 ttl 7476 J-K Flip-Flop logic ic 7476 PDF

    74H73

    Abstract: 9H73 U202 ScansUX997
    Text: FAIRCHILD HIGH SPEED TTL/SSI . 9H73/54H73, 74H73 DUAL JK MASTER/SLAVE FLIP-FLOP WITH SEPARATE CLEARS AND CLOCKS DESCRIPTION — The HSTTL/SSI 9H 73/54 H 7 3 , 74H73 is a High Speed Dual JK Master/Slave flip-flop with separate clears and separate clocks. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the circuitry which connects the master


    OCR Scan     		9H73/54H73, 74H73 9H73 U202 ScansUX997 PDF

    AC109

    Abstract: 5D2 6 54ACT 74AC ACT74
    Text: AC109 • ACT 109 54 AC/74 AC 109 • 54ACT/74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Description Connection Diagrams The ’AC/’ACT109 c o n sists o f tw o high-speed co m p le te ly independent tra n sitio n clo cked JK flip ­ flo p s. The clo ckin g operation is independent o f


    OCR Scan     		ACT109 54AC/74AC109 54ACT/74ACT109 ACT109 ACT74 54/74AC/ACT AC109 5D2 6 54ACT 74AC PDF

    54ACT112

    Abstract: ACT112 E20A J16A
    Text: S e p te m b e r 1 9 9 8 54 ACT 112 Dual JK Negative Edge-Triggered Flip-Flop General Description A s y n c h ro n o u s Inputs: T h e ’A C T 1 1 2 c o n ta in s tw o in d e p e n d e n t, h ig h -s p e e d J K flip -flo p s w ith D ire c t S e t a n d C le a r in p u ts . S y n c h ro n o u s s ta te


    OCR Scan     		54ACT112 ACT112 E20A J16A PDF

    7472 PIN DIAGRAM

    Abstract: 74574 74LS112 74LS74 7473 dual JK 7472 ttl TTL 7472 7472 ci CI 7473 pin diagram of ttl 7476
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE ui 3 Q </> “ UI 0 (9 D50 9000 D51 9001 D54 54/7470 13 2 A zz J So 0 g1 o° CP = Q. 1 H H (0 2 O O Q. EDGE-TRIGGERED ¡so J. So O « J. S d 0 —6 CP J . KC Äo Qo -n — J— K Q CD Vcc = Pin 14


    OCR Scan     		19-olâ 54H/74H71 54H/74H101 54H/74H72 54H/74H102 54H/74H73 54H/74H103 54S/74S113 54LS/74LS113 54H/74H76 7472 PIN DIAGRAM 74574 74LS112 74LS74 7473 dual JK 7472 ttl TTL 7472 7472 ci CI 7473 pin diagram of ttl 7476 PDF

    TTL 74ls74

    Abstract: 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 5 ui 9 D UJ -=pi (3 J Q 2 — J SD 0 CP Z o (3 4 K Ä Co “LT in > </> O a 3 -0 K Co ° I- 3 a. I- 3 O 4-0 Co ? 15 D61 54/7474, 54H/74H74,


    OCR Scan     		54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54H/74H73 54H/74H103 54S/74S113 54LS/74LS113 TTL 74ls74 74ls74 CI 7473 TTL 7474 7476 JK ttl 7474 14 PIN Jk 7476 7474 PIN DIAGRAM pin diagram 7474 7474 16 PIN PDF

    7472 PIN DIAGRAM

    Abstract: 74ls112 pin diagram 74LS112 TTL 74107 74LS74 7473 pin diagram 74h106 7476 CI 7473 Jk 7476
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 A 4 — J. 9— 10 So « Q — 2 J U» CP o 1— CD 0—3 ¿ So Q CP 8_ K Ä Q Co —I I_ Vcc = Pin 14 GND = Pin 7 in Ü Q UJ EDGE-TRIGGERED 9 O (9 D58 54H/74H106 D59b 54H/74H108


    OCR Scan     		54H/74H78 54H/74H106 54S/74S112, 54LS/74LS112 54H/74H108 54S/74S113, 54LS/74LS113 54H/74H73 54H/74H103 54S/74S113 7472 PIN DIAGRAM 74ls112 pin diagram 74LS112 TTL 74107 74LS74 7473 pin diagram 74h106 7476 CI 7473 Jk 7476 PDF

    CI 7474

    Abstract: CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -TTL MASTER/SLAVE EDGE-TRIGGERED D55 9020 D60 9024, 54/74109, 54S/74S109, 54LS/74LS109 ui 9 D UJ 5 -=pi (3 J Q 2 — J SD 0 CP Z o (3 11 4 K Ä 0 Co “LT in > _6 12 CP 3 -0 14 K Co ° 7 o-i- CP 13 —c K Cd °


    OCR Scan     		54S/74S109, 54LS/74LS109 54H/74H74, 54S/74S74, 54LS/74LS74 54H/74H73, 54LS/74LS279 93L14 54LS/74LS196 54LS/74LS197 CI 7474 CI 7473 ci 7476 7474 D latch CI 74LS76 CI 74107 TTL 74ls76 fairchild 9024 ci 74LS74 74ls107 PDF

    CI 74LS90

    Abstract: ci 74193 ci 74ls193 CI 74196 ci 7492 CI 74176 74LS93 TTL 74293 TTL 7493A sn 7492 ttl
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIG ITAL-TTL D121 54/7490A, 54LS/74LS90 D122 54/7492, 74LS92 D123 S4/74293, 54LS/74LS293 6 7 141 Vcc = Pin 5 GND = Pin 10 NC = Pin 4,13 - Vcc = Pin 5 GND = Pin 10 NC = 2, 3, 4, 13 D124 S4/7493A, 54LS/74LS93 D125 54/74176, 54/74177,


    OCR Scan     		54/7490A, 54LS/74LS90 74LS92 S4/74293, 54LS/74LS293 S4/7493A, 54LS/74LS93 93L10, 93S10, 93L16, CI 74LS90 ci 74193 ci 74ls193 CI 74196 ci 7492 CI 74176 74LS93 TTL 74293 TTL 7493A sn 7492 ttl PDF

    d146

    Abstract: RS latch 74LS78 74LS114 7475 D latch d147 CI 74196 74LS112 7475 data latch fairchild 9314
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL MASTER/SLAVE D59a 54H/74H78 13 A « — 2 4— J. So Q 9— J Q U » CP CP o 1— 10 ¿ So CD 0—3 8_ K Ä Q Co —I I_ Vcc = Pin 14 GND = Pin 7 in Ü Q UJ EDGE-TRIGGERED 9 O (9 D58 54H/74H106 D59b 54H/74H108


    OCR Scan     		54H/74H78 54H/74H106 54S/74S112, 54LS/74LS112 54H/74H108 54S/74S113, 54LS/74LS113 54LS/74LS279 93L14 54LS/74LS196 d146 RS latch 74LS78 74LS114 7475 D latch d147 CI 74196 74LS112 7475 data latch fairchild 9314 PDF

    7475 D latch

    Abstract: D146 D147 ci 7475 rs latch 74LS109 74LS78 74LS107 74LS114 7475 data latch
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 j b j j j F5I Fä| F I j j j SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI l i l LiJ L il L iT I U LzJ Ll I ü ü bsJ QNO 9 3 4 li


    OCR Scan     		54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 54LS/74LS279 93L14 7475 D latch D146 D147 ci 7475 rs latch 74LS109 74LS78 74LS107 74LS114 7475 data latch PDF

    logic ic 7476 pin diagram

    Abstract: logic ic 74LS76 pin diagram ic 74109 74LS107 74109 dual JK IC 74196 7476 Connection diagram 74LS109 ic 7474 pin diagram 7474 D latch
    Text: IO PO 10 ro o CO 00 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch - o to Item 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit D Latch 4-Bit RS Latch 4-Bit RS Latch 4-Bit RS Latch 4-Bit RS Latch 5477 54/7475 93L14 9314


    OCR Scan     		54LS/74LS77 54LS/74LS75 54LS/74LS197 93L14 54LS/74LS196 54LS/74LS279 54H/74H73, 54LS/74LS73 54LS/74LS107 logic ic 7476 pin diagram logic ic 74LS76 pin diagram ic 74109 74LS107 74109 dual JK IC 74196 7476 Connection diagram 74LS109 ic 7474 pin diagram 7474 D latch PDF

    74LS47 pin configuration

    Abstract: 7 SEGMENT DISPLAY cd 4511 7447 7-segment display pin diagram decoder 4511 7 segment common anode decoder 74ls47 pin configuration of dual 7-segment led 7 segment ,74LS245 CMOS BCD-to-7-Segment LED Latch Decoder Drivers bcd to 7 segment j-k flip-flop 4511 7447 pin configuration
    Text: FAIRCHILD LO G IC /C O N N EC TIO N DIAGRAMS DIGITAL-CMOS C109 4708B 40 5 - 11 7 12 83539- 3 2 1 34 33 32 11 12 13 14 15 16 17 18 19 20 S T R B T 0 T 1 T 2 T s MWo MW 2 B A o B A2 BA4 BAe BAs 10 MWi B A i BA3 BA5 BA/ BAs 6- 4 C110 4076B =slD 13 12 11 Do D1


    OCR Scan     		4708B 4076B 4511B 4S43B 4734B 4538B C115e 40160B 40161B 40162B 74LS47 pin configuration 7 SEGMENT DISPLAY cd 4511 7447 7-segment display pin diagram decoder 4511 7 segment common anode decoder 74ls47 pin configuration of dual 7-segment led 7 segment ,74LS245 CMOS BCD-to-7-Segment LED Latch Decoder Drivers bcd to 7 segment j-k flip-flop 4511 7447 pin configuration PDF

    ic 74 LS 138 DECODER

    Abstract: Alu 181 8 bit bcd adder/subtractor f245 motorola lal 2084 TTL 74-series IC LIST internal circuitry for sr flip flop T flip flop IC LS248 4-bit bcd subtractor
    Text: SG 6 0R 4 Schottky TTL • O v e r 180 LS Devices • ALS • FAST • TTL C o m p a tib le M acrocell A rra y s • RAMs • PR O M s 006844 /y err This Material Copyrighted By Its Respective Manufacturer General Inform ation TTL in Perspective proved speed — p o w e r product co m p ared to LS as a


    OCR Scan     		SG60R4 16-by-4 ic 74 LS 138 DECODER Alu 181 8 bit bcd adder/subtractor f245 motorola lal 2084 TTL 74-series IC LIST internal circuitry for sr flip flop T flip flop IC LS248 4-bit bcd subtractor PDF

    MUX 74157

    Abstract: 74157 mux 74153 mux mux 74153 74298 quad 2 in mux ttl 74157 TTL 74153 MUX 74151 pin diagram of 74153 74153 8bit
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL -T T L D154 54/74170, 54LS/74LS170, 54LS/74LS670 12 15 1 2 3 H I M Ew Dl Ü2 D156 54/74298, 54LS/74LS298 D155 9309, 93L09 12 11 10 D3 9 4 5 6 7 3 1 3 - So 5 - Ra 3 - Si 6 o o o ec UJ 7 N N 14 15


    OCR Scan     		54LS/74LS170, 54LS/74LS670 93L09 54LS/74LS298 93L22, 54S/74S157, 54LS/74LS157, 54S/74S158, 54LS/74LS158, 54S/74S257 MUX 74157 74157 mux 74153 mux mux 74153 74298 quad 2 in mux ttl 74157 TTL 74153 MUX 74151 pin diagram of 74153 74153 8bit PDF

    FZK101

    Abstract: FZK105 upd101 SNF10 SN76131 TAA700 FZH111 FZJ101 MFC8010 MFC8001
    Text: HANDBOOK OF INTESBATEI CIRCUITS in EQUIVALENTS AND SUBSTITUTES A lthough every care is taken with the preparation of this book, the publishers will not be responsible for any errors that might occur. I.S.B.N. 0 900162 35 X 1974 by Bernard B. Babani First Published 1974


    OCR Scan     		Grou19 CN127-128-638 ZN220-320. CN131-132-642. ZN221-321. CN133-134-644. ZN248-348. CN135-136-646 ZN222-322. CN121-122-682. FZK101 FZK105 upd101 SNF10 SN76131 TAA700 FZH111 FZJ101 MFC8010 MFC8001 PDF

    diode 51X

    Abstract: JK fairchild IQH12 ScansUX978
    Text: P R E LIM IN A R Y DATASHEET • DECEMBER 1 9 6 7 A FAIRCHILD COMPATIBLE C U R R E N T S IN K I N G LOGIC PRODUCT GENERAL D ESCR IPTIO N T h e 9022 c o n s i s t s of tw o J K f lip - f lo p s w ith a c o m m o n c lo c k , s e p a r a t e J a n d K in p u ts a n d a c o m m o n


    OCR Scan     		RESTRiCTEO-23 diode 51X JK fairchild IQH12 ScansUX978 PDF

    74ls373 parallel port

    Abstract: d92 02 74175 ttl pin diagram 74198 74ls175 pin diagram 74198 ttl 74LS374 D172 D173 9z17
    Text: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D82 54LS/74LS78 D81 54LS/74LS541 V cc |S5| RSj FSI F7| F»l FS1 F5I Fä| F I jjjjj j j b SD SD J Q J C CP Q — e Q 5— 9 CP K >— 12 Q K CD CD LlI l i l LiJ L il L iT I U LzJ Ll I üü bsJ QNO 9 3 4 5 D85


    OCR Scan     		54LS/74LS541 54LS/74LS78 54LS/74LS168, 54LS/74LS169 54LS/74LS490 54LS/74LS373 54LS/74LS374 54LS/74LS256 /74LS573 93L34 74ls373 parallel port d92 02 74175 ttl pin diagram 74198 74ls175 pin diagram 74198 ttl 74LS374 D172 D173 9z17 PDF

    fairchild 9000-series

    Abstract: Fairchild 9020 JK flipflop 9001 a9005 9003XM TTL 9020 pin diagram for all 74 series ttl gates ScansUX984 DIODE CQ 521 cd 9017
    Text: FAIRCHILD SERIES TTL/SSI ABSOLUTE M A X IM U M RA TIN G S above which the useful life may be impaired Storage Temperature Temperature (Ambient) UnderBias V c c P'n Potential to Ground Pin * Input Voltage (dc) * Input Current (dc) Voltage Applied to Outputs (Output HIG H)


    OCR Scan     		9N/54/74 fairchild 9000-series Fairchild 9020 JK flipflop 9001 a9005 9003XM TTL 9020 pin diagram for all 74 series ttl gates ScansUX984 DIODE CQ 521 cd 9017 PDF