als240a
Abstract: LS240 244A a244a DV74LS244
Text: 240, 241, 244 AVG DDiT Semiconductors Technical Data DV74LS240 DV74ALS240A DV74LS241 DV74ALS241A DV74LS244 DV74ALS244A 3-State Octal Buffers/Inverters Line Drivers The DV74LS240, DVALS240A, DV74LS241, DV74ALS241A, DV74LS244 and DV74ALS244A are Octal Buffers and Line Drivers de
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DV74LS240,
DVALS240A,
DV74LS241,
DV74ALS241A,
DV74LS244
DV74ALS244A
DV74LS240
DV74ALS240A
DV74LS241
DV74ALS241A
als240a
LS240
244A
a244a
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74ls652
Abstract: 74LS654 L8651 74LS653 LS652 SN74LS654 SN54LS651JS
Text: 8 -Bit Bus Front-Loading-Latch Transceivers SN54/74LS652 SN54/74LS654 SN54/74LS651 SN54/74L.S653 Ordering Information Features/Benefits • Bidirectional bus transceivers and registers • Independent registers tor A and B buses PART NUMBER PKG TEMP POLARITY OUTPUTS POWER
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SN54/74LS651
SN54/74LS652
SN54/74LS653
SN54/74LS654
24-pin
LS653/4
LS651,
LS652)
LS653,
LS654)
74ls652
74LS654
L8651
74LS653
LS652
SN74LS654
SN54LS651JS
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a8j1
Abstract: 54LS642 smd code Yj 33
Text: REVISIONS LTR DATE VR-MO-DA DESCRIPTION APPROVED REV SHEET REV SHEET REV STATUS OF SHEETS REV SHEET 3 PMIC N/A P R K A R E D BY STANDARDIZED MILITARY DRAWING CH ECK ED BY THIS ORAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES O F THE DEPARTMENT O F D EFEN SE
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5962-E1640
5962-8974801RX
SNJ54LS642J
5962-8974801SX
SNJ54LS642W
5962-89748012X
SNJ54LS642FK
a8j1
54LS642
smd code Yj 33
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74LS373PC
Abstract: 74LS373P e10s LOGIC DESCRIPTION OF 74LS373 LS 373 74LS373DC 54LS373DM 54LS373FM 74LS373FC 74LS373D
Text: 373 CONNECTIO N DIAGRAM PINOUT A / 54LS/74LS373 OCTAL TRANSPARENT LATCH W ith 3-S tate Outputs OE [7 Ü3 Vcc Oo U ï ï) 1 0 7 Do [ 2 jÜ D ? Di [7 13 De 01 [T ïi)0 6 02 (T 1 5 ] 05 Ds [ 7 ï ï d 3 [T 13] d » o 3 |T T U 04 G ND ¡10 DESCRIPTION — The ’373 consists o f eight latches w ith 3-state outputs for
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54LS/74LS373
74LS373PC
74LS373DC
74LS373FC
54/74LS
74LS373PC
74LS373P
e10s
LOGIC DESCRIPTION OF 74LS373
LS 373
74LS373DC
54LS373DM
54LS373FM
74LS373FC
74LS373D
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Untitled
Abstract: No abstract text available
Text: Programmable Array Logic PAL Description The PAL® family utilizes National Semicon ductor’s Schottky TTL process and bipolar PROM fusible-link technology to provide user-programmable logic to replace conven tional SSI/MSI gates and flip-flops. Typical
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LS173A
Abstract: No abstract text available
Text: AVG Semiconductors _ DPi Technical Data 173 DV74LS173A DV74ALS173A 4-Bit D-Type Register with 3-State Outputs This dovico is a high-speed 4-Bit Register featuring 3-state outputs for uso in bus-organized systems. The clock is fully edge-triggered
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DV74LS173A
DV74ALS173A
AVG-003
AVG-004
DV74LS173A,
DW4ALS173A
1-800-AVG-SEMI
LS173A
ALS173A
1-800-AV6-SEMI
LS173A
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OE1T
Abstract: ALS299
Text: 299, 323 AVG Semiconductors _ DDT Technical Data DV74LS299 DV74ALS299 DV74LS323 DV74ALS323 8-Bit Universal Shift/Storage Register with 3-State Outputs These devices have four possible modes of operation: hold, shift left, shift right and load data. Clearing occurs asynchronously on LS299,
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LS299,
ALS299,
LS323,
ALS323.
DV74LS299-323,
DV74ALS299-323
1-800-AVG-SEMI
OE1T
ALS299
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