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    74HCT11 Search Results

    74HCT11 Result Highlights (4)

    Part ECAD Model Manufacturer Description Download Buy
    CD74HCT11M96E4 Texas Instruments High Speed CMOS Logic Triple 3-Input AND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT11M96 Texas Instruments High Speed CMOS Logic Triple 3-Input AND Gates 14-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT11E Texas Instruments High Speed CMOS Logic Triple 3-Input AND Gates 14-PDIP -55 to 125 Visit Texas Instruments Buy
    CD74HCT112E Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125 Visit Texas Instruments Buy
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    74HCT11 Price and Stock

    Nexperia 74HCT11PW-Q100J

    IC GATE AND 3CH 3-INP 14TSSOP
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    DigiKey 74HCT11PW-Q100J Digi-Reel 6,392 1
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    74HCT11PW-Q100J Reel 2,500 2,500
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    Mouser Electronics 74HCT11PW-Q100J 3,094
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    Rochester Electronics 74HCT11PW-Q100J 20,000 1
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    Nexperia 74HCT11PW,118

    IC GATE AND 3CH 3-INP 14TSSOP
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    DigiKey 74HCT11PW,118 Digi-Reel 4,536 1
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    Mouser Electronics 74HCT11PW,118 1,689
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    Arrow Electronics 74HCT11PW,118 7,500 846
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    Rochester Electronics 74HCT11PW,118 3,940 1
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    Nexperia 74HCT11D-Q100J

    IC GATE AND 3CH 3-INP 14SO
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    DigiKey 74HCT11D-Q100J Cut Tape 2,117 1
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    Avnet Americas 74HCT11D-Q100J Reel 8 Weeks 7,500
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    Mouser Electronics 74HCT11D-Q100J 1,990
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    Texas Instruments CD74HCT112E

    IC FF JK TYPE DUAL 1BIT 16DIP
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    DigiKey CD74HCT112E Tube 499 1
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    Mouser Electronics CD74HCT112E 817
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    Bristol Electronics CD74HCT112E 190
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    Rochester Electronics CD74HCT112E 12,422 1
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    Texas Instruments CD74HCT11M

    IC GATE AND 3CH 3-INP 14SOIC
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    DigiKey CD74HCT11M Tube 316 1
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    Find more 74HCT11 price and stock on Findchips.com

    74HCT11 Datasheets (56)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74HCT11 Philips Semiconductors Triple 3-Input AND Gate Original PDF
    74HCT112 Philips Semiconductors negative-edge trigger Original PDF
    74HCT112D Philips Semiconductors dual JK flip-flop with set and reset negative-edge trigger Original PDF
    74HCT112D Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HCT112D,652 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT109-1 (SO16); Container: Bulk Pack, CECC Original PDF
    74HCT112D,653 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13", CECC Original PDF
    74HCT112DB Philips Semiconductors dual JK flip-flop with set and reset negative-edge trigger Original PDF
    74HCT112DB Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HCT112DB,112 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT338-1 (SSOP16); Container: Tube Original PDF
    74HCT112DB,118 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13" Original PDF
    74HCT112DB-T NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V Original PDF
    74HCT112DB-T Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HCT112D-T NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V Original PDF
    74HCT112D-T Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HCT112N Philips Semiconductors Dual JK flip-flop with set and reset, negative-edge trigger Original PDF
    74HCT112N Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HCT112N,652 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT38-4 (DIP16); Container: Bulk Pack, CECC Original PDF
    74HCT112PW Philips Semiconductors dual JK flip-flop with set and reset negative-edge trigger Original PDF
    74HCT112PW Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74HCT112PW,112 NXP Semiconductors dual JK flip-flop with set and reset; negative-edge trigger - Description: Dual J-K Flip-Flop with Set and Reset; Negative-Edge Trigger; TTL Enabled ; Fmax: 70 MHz; Logic switching levels: TTL ; Output drive capability: +/- 4 mA ; Power dissipation considerations: Low Power ; Propagation delay: 19 ns; Voltage: 4.5-5.5V; Package: SOT403-1 (TSSOP16); Container: Tube Original PDF

    74HCT11 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    IC 74HC112

    Abstract: 74HC112
    Text: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141A Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2000


    Original     		PDF CD54/74HC112, CD54/74HCT112 SCHS141A HC112 HCT112 loSZZU001B, SDYU001N, SCET004, SCAU001A, CD74HC112E IC 74HC112 74HC112

    74HCT112N

    Abstract: No abstract text available
    Text: 970721 01 SIDA: 1/5 ELFA artikelnr. 73-516-38 74HCT112N logikkrets 970721 01 SIDA: 2/5 970721 01 SIDA: 3/5 970721 01 SIDA: 4/5 970721 01 SIDA: 5/5


    Original     		PDF 74HCT112N

    74hc11

    Abstract: No abstract text available
    Text: 74HC11; 74HCT11 Triple 3-input AND gate Rev. 5 — 16 December 2011 Product data sheet 1. General description The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .


    Original     		PDF 74HC11; 74HCT11 74HCT11 74HC11: 74HCT11: JESD22-A114F JESD22-A115-A 74hc11

    74HCT11

    Abstract: 74hc11
    Text: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54/74HC11, CD54/74HCT11 Data sheet acquired from Harris Semiconductor SCHS273A High Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised May 2000 Features Description • Buffered Inputs


    Original     		PDF CD54/74HC11, CD54/74HCT11 SCHS273A HCT11 SDYA012 SN54/74HCT SCLA011 SCLA008 SZZU001B, SDYU001N, 74HCT11 74hc11

    74hc11

    Abstract: No abstract text available
    Text: 74HC11-Q100; 74HCT11-Q100 Triple 3-input AND gate Rev. 2 — 22 March 2013 Product data sheet 1. General description The 74HC11-Q100; 74HCT11-Q100 is a triple 3-input AND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in


    Original     		PDF 74HC11-Q100; 74HCT11-Q100 74HCT11-Q100 AEC-Q100 74HC11-Q100: 74HCT11-Q100: 74hc11

    74HC112

    Abstract: data sheet IC 74HC112 CD54HC112F3A CD54HCT112F3A CD74HC112E CD74HC112NSR
    Text: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141B Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised March 2002


    Original     		PDF HC112 HCT11 CD54/74HC112, CD54/74HCT112 SCHS141B HC112 HCT112 74HC112 data sheet IC 74HC112 CD54HC112F3A CD54HCT112F3A CD74HC112E CD74HC112NSR

    HCT114

    Abstract: 74HC11 datasheet 74hc11 74HC11D 74HC11DB 74HC11N 74HCT11 74HCT11D 74HCT11DB 74HCT11N
    Text: 74HC11; 74HCT11 Triple 3-input AND gate Rev. 04 — 25 March 2010 Product data sheet 1. General description The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .


    Original     		PDF 74HC11; 74HCT11 74HCT11 74HC11: 74HCT11: JESD22-A114F JESD22-A115-A HCT114 74HC11 datasheet 74hc11 74HC11D 74HC11DB 74HC11N 74HCT11D 74HCT11DB 74HCT11N

    74HC11

    Abstract: 74HCT11 74HC11D 74HC11N 74HCT11D 74HCT11DB 74HCT11N 74HC11DB 74HCT11N pin diagram 74HCT11P
    Text: 74HC11; 74HCT11 Triple 3-input AND gate Rev. 03 — 9 February 2010 Product data sheet 1. General description The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL LSTTL .


    Original     		PDF 74HC11; 74HCT11 74HCT11 74HC11: 74HCT11: JESD22-A114F JESD22-A115-A 74HC11 74HC11D 74HC11N 74HCT11D 74HCT11DB 74HCT11N 74HC11DB 74HCT11N pin diagram 74HCT11P

    74HC112

    Abstract: IC 74HC112
    Text: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141C Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised July 2002


    Original     		PDF CD54/74HC112, CD54/74HCT112 SCHS141C HC112 HCT11 74HC112 IC 74HC112

    CD54HC112F3A

    Abstract: CD54HCT112F3A CD74HC112E CD74HCT112E IC 74HC112 74HC112
    Text: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141A Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised May 2000


    Original     		PDF HC112 HCT11 CD54/74HC112, CD54/74HCT112 SCHS141A HC112 HCT112 CD54HC112F3A CD54HCT112F3A CD74HC112E CD74HCT112E IC 74HC112 74HC112

    HC Cmos Logic 74Hc11

    Abstract: No abstract text available
    Text: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54/74HC11, CD54/74HCT11 Data sheet acquired from Harris Semiconductor SCHS273A High Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised May 2000 Features Description • Buffered Inputs


    Original     		PDF HCT11 CD54/74HC11, CD54/74HCT11 SCHS273A HCT11 HC Cmos Logic 74Hc11

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD54 HCT11 , CD74 HC11, CD74 HCT11 /Subject (High CD54/74HC11, CD54/74HCT11 Data sheet acquired from Harris Semiconductor SCHS273A High Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised May 2000 Features Description • Buffered Inputs


    Original     		PDF CD54/74HC11, CD54/74HCT11 SCHS273A HCT11 59628970901CA CD54HCT11F CD54HCT11F3A 5962View 8970901CA

    8408801EA

    Abstract: No abstract text available
    Text: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141E Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised January 2003


    Original     		PDF CD54/74HC112, CD54/74HCT112 SCHS141E HC112 HCT112 59628970201EA CD54HCT112F3A 5962View 8970201EA 8408801EA

    Untitled

    Abstract: No abstract text available
    Text: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141E Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised January 2003


    Original     		PDF CD54/74HC112, CD54/74HCT112 SCHS141E HC112 HCT112

    IC 74HC112

    Abstract: HC112
    Text: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141B Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised March 2002


    Original     		PDF CD54/74HC112, CD54/74HCT112 SCHS141B HC112 HCT112 SDYZ001A, CD74HC112E CD74HC112M96 CD74HC112NSR CD74HC112PWR IC 74HC112

    74ls112 pin diagram

    Abstract: 74HC112
    Text: GD54/74HC112, GD54/74HCT112 DUAL J-K FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 54/74LS112. They consist of two J-K flip-flops with individual J, K, CLOCK, PRESET, and CLEAR in­ puts. These flip-flops are edge sensitive to the clock


    OCR Scan     		PDF GD54/74HC112, GD54/74HCT112 54/74LS112. 74ls112 pin diagram 74HC112

    74hct11m

    Abstract: 74hc11
    Text: Technical Data CD54/74HC11 CD54/74HCT11 File N um ber 1475 High-Speed CMOS Logic Triple 3-Input AND Gate Type Features: • B utte red inpu ts ■ Typical propagation delay = 8 ns @ VCc - 5 V, CL = 15 pF, 7« = 25° C T E R M IN A L A S S IG N M E N T The R C A-CD54/74HC11 and C D 54/74HCT11 lo gic gates


    OCR Scan     		PDF CD54/74HC11 CD54/74HCT11 -CD54/74HC11 54/74HCT11 54LS/74LS CD54HC11 CD54HCT11 92CS-36 972R5 54/74H 74hct11m 74hc11

    74hc11

    Abstract: No abstract text available
    Text: \ - + Technical Data CD54/74HC11 CD54/74HCT11 HARRIS SEMICOND 3 -2- 1-00 File N um b er SECTOR 27E D H 4302271 1475 001747= 2 • H A S High-Speed CMOS Logic Triple 3-Input AND Gate Type Features: ■ B uffe red inputs m Typical propagation delay = 8 ns r A = 25° c


    OCR Scan     		PDF CD54/74HC11 CD54/74HCT11 -CD54/74HC11 CD54/74HCT11 T/74H 54/74HC 54/74HCT 74hc11

    GD74HC11

    Abstract: No abstract text available
    Text: GD54/74HC11, GD54/74HCT11 TRIPLE 3-INPUT AND GATES General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 1 . They contain three independent 3-input AND gates. These devices are characteriz­ ed for operation over wide temperature ranges to


    OCR Scan     		PDF GD54/74HC11, GD54/74HCT11 GD74HC11

    74hc113

    Abstract: 74HCT113 GD74HCT11 74HC GD54HC113 GD74HC113 74LS113
    Text: GD54/74HC113, GD54/74HCT113 DUAL J-K FLIP-FLOPS WITH PRESET General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 13. They consist of two J-K flip-flops with individual J, K, Clock, and Preset inputs. These flip-flops are edge sensitive to the clock input and


    OCR Scan     		PDF GD54/74HC113, GD54/74HCT113 54/74LS113. 74hc113 74HCT113 GD74HCT11 74HC GD54HC113 GD74HC113 74LS113

    Untitled

    Abstract: No abstract text available
    Text: Technical Data CD54/74HC11 CD54/74HCT11 File N um ber 1475 High-Speed CMOS Logic Triple 3-Input AND Gate Type Features: • B u ffe re d inputs ■ Typical propagation delay - 8 ns < ' Vcc = 5 V , C L = 15 pF, 7a = 25° C T E R M IN A L A S S IG N M E N T


    OCR Scan     		PDF CD54/74HC11 CD54/74HCT11 54/74H 54/74HCT11 T/74H 54LS/74LS CD54HC11 CD54HCT1 92CS-36972R5 54/74HC

    CD54HC112

    Abstract: CD54HCT112 CD74HC112 CD74HCT112 74hct112
    Text: Technical Data CD54/74HCT112 CD54/74HCT112 HARRIS S E M I C O N D File N um b er 27E T> SE CTO R High-Speed CMOS Logic 1843 Hi 4302271 0017551 h B H A S T - ^ - 1 - 1 Dual J-K Flip-Flop with Set and Reset N e g a t iv e - E d g e T r ig g e r T y p e Featu res:


    OCR Scan     		PDF CD54/74HCT112 CD54/74HCT112 92cs-40j4i RCA-CD54/74HC112 92CS-39232 92CS-39233RI 92CS-39234 54/74HCT CD54HC112 CD54HCT112 CD74HC112 CD74HCT112 74hct112

    Untitled

    Abstract: No abstract text available
    Text: Technical Data CD54/74HCT112 CD54/74HCT112 File N um ber 1843 High-Speed CMOS Logic Dual J-K Flip-Flop with Set and Reset N e g a tiv e -E d g e T rig g e r Type Features: • H ysteresis on c lo c k inpu ts lo r im proved noise im m u n ity a n d increased


    OCR Scan     		PDF CD54/74HCT112 S-4034I 54/74H 54/74HC

    Untitled

    Abstract: No abstract text available
    Text: Technical Data CD54/74HCT112 CD54/74HCT112 File Number 1843 High-Speed CMOS Logic Dual J-K Flip-Flop with Set and Reset N egative-Edge Trig g er Type Features: • H ysteresis on clo ck inputs for improved noise immunity and increased input rise and tail times


    OCR Scan     		PDF CD54/74HCT112 RCA-CD54/74HC112 54/74HCT