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    74AC11010 Price and Stock

    Texas Instruments 74AC11010N

    IC,LOGIC GATE,3 3-INPUT NAND,AC-CMOS,DIP,16PIN,PLASTIC
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    Quest Components 74AC11010N 174
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    Signetics 74AC11010N

    IC,LOGIC GATE,3 3-INPUT NAND,AC-CMOS,DIP,16PIN,PLASTIC
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    Quest Components 74AC11010N 10
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    Texas Instruments 74AC11010D

    INSTOCK
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    Chip 1 Exchange 74AC11010D 1,000
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    NXP Semiconductors 74AC11010N

    NAND GATE; Temperature Grade: INDUSTRIAL; Terminal Form: THROUGH-HOLE; No. of Terminals: 16; Package Code: DIP; Package Shape: RECTANGULAR;
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    Vyrian 74AC11010N 293
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    74AC11010 Datasheets (7)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    74AC11010 Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATES Original PDF
    74AC11010 Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATES Original PDF
    74AC11010D Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATE Original PDF
    74AC11010D Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF
    74AC11010DR Texas Instruments Triple 3-Input Positive-NAND Gates Original PDF
    74AC11010N Texas Instruments TRIPLE 3-INPUT POSITIVE-NAND GATE Original PDF
    74AC11010N Unknown Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. Historical PDF

    74AC11010 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    54AC11010

    Abstract: 74AC11010
    Text: 54AC11010, 74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCLS057 – MAY 1987 – REVISED APRIL 1993 • • • • • 54AC11010 . . . J PACKAGE 74AC11010 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations


    Original     		54AC11010, 74AC11010 SCLS057 54AC11010 500-mA 300-mil 54AC11010 74AC11010 PDF

    54AC11010

    Abstract: 74AC11010
    Text: 54AC11010, 74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCLS057 – MAY 1987 – REVISED APRIL 1993 • • • • • 54AC11010 . . . J PACKAGE 74AC11010 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations


    Original     		54AC11010, 74AC11010 SCLS057 54AC11010 500-mA 300-mil 54AC11010 74AC11010 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11010, 74AC11010 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES ăą SCLS057 − MAY 1987 − REVISED APRIL 1993 • • • • • 54AC11010 . . . J PACKAGE 74AC11010 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations


    Original     		54AC11010, 74AC11010 SCLS057 54AC11010 500-mA 300-mil PDF

    54AC11010

    Abstract: 74AC11010
    Text: 54AC11010, 74AC11010 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES ăą SCLS057 − MAY 1987 − REVISED APRIL 1993 • • • • • 54AC11010 . . . J PACKAGE 74AC11010 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations


    Original     		54AC11010, 74AC11010 SCLS057 54AC11010 500-mA 300-mil 54AC11010 74AC11010 PDF

    S2-34

    Abstract: No abstract text available
    Text: 54AC11010, 74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES TI0048— D2957, M AY 1987—R EVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11010 . . . J PACKAGE 74AC11010 . . . 0 OR N PACKAGE TOP VIEW • Center-PIn Vq c and GND Configurations to


    OCR Scan     		54AC11010, 74AC11010 TI0048-- D2957, 1987--R 500-mA 300-mil 54AC11010 S2-34 PDF

    54AC11010

    Abstract: 74AC11010 D2957
    Text: 54AC11010, 74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES TI0048— D2957, MAY 1987—REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11010 . . . J PACKAGE 74AC11010 . . . D O R N PACKAGE TOP VIEW Center-Pin V q C and GND Configurations to


    OCR Scan     		54AC11010, 74AC11010 TI0048â D2957, 500-mA 300-mil 54AC11010 74AC11010 D2957 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11010,74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES D2957, MAY 1987 - REVISED APRIL 1993 • ■ * Flow-Through Architecture Optimizes PCB Layout I I • Center-Pin Vqq and GND Configurations Minimize High-Speed Switching Noise | • EPIC'" Enhanced-Performance Implanted


    OCR Scan     		54AC11010 74AC11010 D2957, 500-mA 300-mil 54AC11010 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11010,74AC11010 TRIPLE 3-INPUT POSITIVE-NAND GATES D2957, MAY 1987 - REVISED APRIL 1983 Flow-Through Architecture Optimizes PCB Layout Center-PIn Vqc and GND Configurations Minimize High-Speed Switching Noise EP IC “ Enhanced-Performance Implanted CMOS 1-|j.m Process


    OCR Scan     		54AC11010 74AC11010 D2957, 500-mA 300-mll PDF