Untitled
Abstract: No abstract text available
Text: CD4014BM CD4014BC 8-Stage Static Shift Register General Description Dual-In-Line Package Features Y Y Y Y Y Y Wide supply voltage range 3 0V to 15V High noise immunity 0 45 VDD typ Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS 5V – 10V – 15V parametric ratings
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CD4014BM
CD4014BC
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Untitled
Abstract: No abstract text available
Text: 257A INPUT LO ADING /FAN -O U T: See Section 3 for U.L. definitions PIN NAMES Zn . DESCRIPTION 3-State O utputs 54/74LS U.L. HIG H/LO W A* V ' K 65/15 (25)/(7.5) DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (uni ess otherwise specified) SYMBOL 54/74LS
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54/74LS
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74LS
Abstract: CD4015BC CD4015BM 18VQC
Text: CD4015BM/CD4015BC i/W \ National m!m Semiconductor CD4015BM/CD4015BC DUAL 4-BIT Static Shift Register General Description fan ou t o f 2 d rivin g 74L or 1 driving 74LS Low pow er TTL c o m p a tib ility The CD4015BM/CD4015BC c o n ta in s tw o id e n tic a l,
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CD4015BM/CD4015BC
74LS
CD4015BC
CD4015BM
18VQC
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74LS
Abstract: CD4015B CD4015BC CD4015BM J16A
Text: June 1996 CD4015BM/CD4015BC Dual 4-Bit Static Shift Register Features • W ide supply voltage range ■ High noise im m unity ■ Low pow e r TTL com patibility 3.0V to 18V 0.45 V DD typ. Fan o ut o f 2 driving 74L o r 1 driving 74LS ■ M edium speed operation
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CD4015BM/CD4015BC
74LS
CD4015B
CD4015BC
CD4015BM
J16A
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Untitled
Abstract: No abstract text available
Text: October 1987 Revised January 1999 S E M ¡ C O N D U C T O R TM Features • Wide supply voltage range: ■ High noise immunity: 3.0V to 15V 0.45 Vqq typ. ■ Low power TTL compatibility: or 1 driving 74LS ■ New formula: C in Farads) PW 0 ut = RC Fan out of 2 driving 74L
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CD4528BC
CD4538BCM
16-Lead
CD4538BC
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54LS365ADM
Abstract: 54LS365AFM 74LS365ADC 74LS365AFC 74LS365APC 74LS365AD
Text: 365A CONNECTIO N DIAGRAM PINOUT A J 54LS /74LS 365A HEX 3-STATE BUFFER W ith C om m on 2 -In p u t NOR Enable ORDERING CODE: See Section 9 PIN PKGS Plastic DIP <P) Ceramic DIP <D) Flatpak (F ) OUT COM M ERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%, = 0° C t o +70° C
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54LS/74LS365A
74LS365APC
74LS365ADC
74LS365AFC
54LS365ADM
54LS365AFM
54/74LS
54/74LS
54LS365ADM
54LS365AFM
74LS365ADC
74LS365AFC
74LS365APC
74LS365AD
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Untitled
Abstract: No abstract text available
Text: 366A J 54LS /74LS 366A CO NNECTIO N DIAGRAM PINOUT A v/ HEX 3-S T A T E IN VER TER BUFFER W ith C o m m o n 2 -In p u t N O R E n ab le ORDERING CODE: See Section 9 PIN PKGS Plastic DIP (P) OUT A CO M M ERCIAL GRADE M ILITARY GRADE V cc = +5.0 V ±5%, T a = 0°C to + 7 0 °C
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/74LS
74LS366APC
74LS366ADC
54LS366ADM
74LS366AFC
54LS366AFM
54/74LS
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74LS20PC
Abstract: 74LS20 74LS20P pinout 7420 7420PC
Text: 20 CO NNECTIO N DIAGRAMS PINOUT A '54/7420 öf 2 ^ / 54H/74H20 S ' O P ' l l/54S/74S20 0 / 0 / 3 1 ^¿4LS /74LS 20 ¿ ? / r / 3 * DUAL 4-INPUT NAND GATE ORDERING CODE: See Section 9 CO M M ERCIAL GRADE PIN PKGS OUT MILITARY GRADE Vcc = +5.0 V ±5%, Vcc = +5.0 V ±10%,
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54H/74H20
l/54S/74S20
/74LS
7420PC,
74H20PC
74S20PC,
74LS20PC
7420DC,
74H20DC
74S20DC,
74LS20
74LS20P
pinout 7420
7420PC
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Untitled
Abstract: No abstract text available
Text: 273 CO NNECTIO N DIAGRAM PINOUT A 54LS/74LS273 // s ^V 8-BIT REGISTER With Clear DESCRIPTION — The ’273 is a high speed 8-bit register, consisting of eight D-type flip -flo p s w ith a com m on C lock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch
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54LS/74LS273
20-pin
74LS273PC
74LS2735
54/74LS
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7414PC
Abstract: dgb3t IC 7414 74LS14PC
Text: NATIONAL SENICOND -CLOGIO DEE D I bSG1125 I DGb3t,51 2 r-9ß-,r CO NN ECTIO N DIAGRAM PINOUT A 54/7414 5 4LS /74LS 14 HEX SCHMITT TRIGGER INVERTER ORDERING CODE: See Section 9 CO M M ERC IAL GRADE PIN PKGS O UT V cc = +5.0 V ±5%, T a = 0 °C to +70° C
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bSG1125
/74LS
7414PC,
74LS14PC
7414DC,
74LS14DC
7414FC,
74LS14FC
5414DM,
54LS14DM
7414PC
dgb3t
IC 7414
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Untitled
Abstract: No abstract text available
Text: 503 CO NNECTIO N DIAGRAM PINOUT A / 54LS/74LS503 OlllCI3 8-BIT SUCCESSIVE APPROXIMATION REGISTER With Expansion Control DESCRIPTION — The ’LS503 register is_basically the same as the 'LS502 ex cept that it has an active LOW Enable (E) input that is used in cascading two
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54LS/74LS503
LS503
LS502
54/74LS
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Untitled
Abstract: No abstract text available
Text: 26 CO NNECTION DIAGRAM PINOUT A 7426 o / 54LS/74LS26 o > QUAD 2-INPUT NAND BUFFER (With Open-Collector Outputs ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C Vcc = +5.0 V ±10%, Ta = -5 5 °C to +125°C
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54LS/74LS26
7426PC,
74LS26PC
7426DC,
74LS26DC
54LS26DM
7426FC,
74LS26FC
54LS26FM
54/74LS
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Untitled
Abstract: No abstract text available
Text: 133 CO NNECTIO N DIAGRAM PINOUT A J 54S/74S133 O / ô ^ 54LS/74LS133 o / ¿vsW 13-INPUT NAND GATE ORDERING CODE: See Section 9 PIN PKGS O UT CO M M ERCIAL GRADE M ILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C V cc = +5.0 V ±10%, T a = -55° C to +125°C
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54S/74S133
54LS/74LS133
13-INPUT
74S133PC,
74LS133PC
74S133DC,
74LS133DC
74S133FC,
74LS133FC
54S133DM,
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74S113PC
Abstract: 54S113DM
Text: 1 NATIONAL SEfHCOND -CLOGIO DEE D I tiSGllSE DGbBTfii T T ~ *f¿ - 0 7 -0 7 Fl3 CO N N ECTIO N DIAGRAM PINO UT A 54S /74S 113 54LS /74LS113 D UA L JK E D G E -T R IG G E R E D FLIP-FLOP D ESC R IP TIO N — T h e '1 13offers individual J , K, Set and Clock inputs. When
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/74LS113
13offers
S/74LS
54/74S
54/74LS
fl-07
74S113PC
54S113DM
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74LS00P
Abstract: 74LS00 pinout 74LS00 fan-out 74LS00 7400 74S00 7400 fan-out 74LS00PC 7400PC 74LS00 74LS00D 74LS00DC
Text: 00 CO NNECTIO N DIAGRAMS PINOUT A 54/7400 ^ o n et* 54H /74H 00Ä eU9 5 4 S /7 4 S 0 0 ^' /V 54LS/74LS00^'/ bUi QUAD 2-INPUT NAND GATE ORDERING CODE: See Section 9 CO M M ERCIAL GRADE PIN PKGS Vcc = +5.0 V ±5%, = 0° C to +70° C OUT M ILITARY GRADE Vcc = +5.0 V ±10%,
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54H/74H00
54S/74S00
54LS/74LS00^
54/74H
54/74S
54/74LS
7400PC,
74H00PC
74LS00PC,
74S00PC
74LS00P
74LS00 pinout
74LS00 fan-out
74LS00 7400 74S00
7400 fan-out
74LS00PC
7400PC
74LS00
74LS00D
74LS00DC
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NAND Gate 3-Input 7410
Abstract: 74LS10PC
Text: 10 CO NNECTIO N DIAGRAMS PINO UT A '''54/7410 ^é4H/74H10 ^54S/74S10 ö / ' o -h? ^ 4 L S /7 4 L S 1 0 ^ / y 7 TRIPLE 3-INPUT NAND GATE ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE M ILITARY GRADE V cc = +5.0 V ±5%, T a = 0° C to +70° C
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4H/74H10
54S/74S10
7410PC,
74H10PC
74S10PC,
74LS10PC
7410DC,
74H10DC
74S10DC,
74LS10DC
NAND Gate 3-Input 7410
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rs flip-flop IC 7400
Abstract: 74ls105 TTL LS 7400 74LS series logic gates 7400 fan-out 74LS 3 input AND gate IC TTL 7400 schematic 74LS04 fan-out 74ls series logic family 90 watts inverter by 12v dc with 6 transisters
Text: GENERAL DESCRIPTION ABSOLUTE MAXIMUM RATINGS Ovar operating free-air temper ature range unless otherwise noted Supply Voltage Vq c (See Note 1) Input Voltage V|n (See Note 1) Interemitter Voltage (See Note 2) Resistor Node Voltage, 54121, 74121 (See Note 1)
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74174PC
Abstract: 74174
Text: NATIONAL SEMICOND -ELOGIO OPE D | bSDllSB üüb3öfl4 3 | 174 T -4 6 -0 7 -1 0 CO NNECTIO N DIAGRAM PINOUT A 54/74174 54S /74S 174 54LS /74LS 174 1 HEX D FLIP-FLOP DESCRIPTION — The '174 is a high speed hex D flip -flo p. The device is used prim arily as a 6-bit edge-triggered storage register. The inform ation
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/74LS
151vcc
54/74S
54/74LS
74174PC
74174
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IC 7422
Abstract: IC 7422 g 74H22
Text: 22 CO NNECTIO N DIAGRAMS PINOUT A 54/7422 6 / ' ô < / 54H/74H22 > w/ o4S/74S22 o / ¿ 5 v54LS/74LS22 ,v/j> <r DUAL 4-INPUT NAND GATE With O pen-Collector Output ORDERING CODE: See Section 9 COMM ERCIAL GRADE PIN PKGS Vcc = +5.0 V ±5%, = 0 °C to +70° C
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54H/74H22
o4S/74S22
v54LS/74LS22
7422PC,
74H22PC
74S22PC,
74LS22PC
7422DC,
74H22DC
74S22DC,
IC 7422
IC 7422 g
74H22
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7451 ic
Abstract: 54S51 74LS51 74H51PC
Text: 51 CO NNECTIO N DIAGRAMS PINOUT A Offo-pfa 1/^4/7451 v^4H /74H 51 r -h M i S4S/74S51 ' - ’ ^Ö4LS/74LS51 m h ò ' f DUAL 2-WIDE, 2-INPUT AOI GATE DUAL 2-WIDE, 2-INPUT/3-INPUT AOI GATE CLS51 ORDERING CODE: See Section 9 PIN PKGS Plastic DIP P) Ceramic DIP (D)
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S4S/74S51
4LS/74LS51
CLS51)
74H51PC
74S51PC
74LS51PC
74H51DC
74S51DC
74LS51DC
74S51FC
7451 ic
54S51
74LS51
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74LS30PC
Abstract: 74LS30 74LS30P 7430DC
Text: 30 CO NNECTIO N DIAGRAMS PINO UT A 54/7430 o/ô //7 54H/74H30 ò /q /s o W54S/74S30/ , \/54LS/74LS30 O Vcc d 8-INPUT NAND GATE E E E m Œ ]Ö ]N C [7 I] 1 3 ]n C 13 U gnd ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%,
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54H/74H30
W54S/74S30/
\/54LS/74LS30
7430PC,
74H30PC
74S30PC,
74LS30PC
7430DC,
74H30DC
74S30DC,
74LS30
74LS30P
7430DC
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7411 3 INPUT AND gate
Abstract: 74LS11 dm 7411 3 input and gate 7411 74LS11 pinout 7411 and gate 74S11PC 54H11 54S11DM 74H11DC
Text: 11 CO NNECTIO N DIAGRAMS PINOUT A ^ 4 /7 4 1 1 o/fc:- £ L 54H/74H11 3 ^ u54S/74S11 o / / 6 5 3 -54LS/74LS11 TRIPLE 3-INPUT AND GATE ORDERING CODE: See Section 9 PIN PKGS OUT CO M M ERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%, T a = 0°C to +70° C Vcc = +5.0 V ±10%,
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54H/74H11
u54S/74S11
-54LS/74LS11
74H11PC
74S11PC,
74LS11
74H11DC
74S11
54H11
7411 3 INPUT AND gate
dm 7411 3 input and gate
7411
74LS11 pinout
7411 and gate
74S11PC
54S11DM
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IC AND GATE 7408
Abstract: IC 7408 7408 AND fan in 7408 AND GATE fan in 74LS08PC 74LS08P propagation delay ic 74ls08 IC 7408 gate 74LS08 74LS08 fan in
Text: ’ NATIONAL SEMICOND -ELOGIO GEE D | bSG115E DDL3L4S 7 | ' _ T - 08 CO NNECTIO N DIAGRAMS PINO UT A 54/7408 54H/74H08 54S/74S08 54LS/74LS08 QUAD 2-INPUT AND GATE ORDERING CODE: See Section 9 PIN PKGS O UT CO M M ERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%,
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bSG115E
54H/74H08
54S/74S08
54LS/74LS08
7408PC,
74H08PC
74S08PC,
74LS08PC
7408DC,
74H08DC
IC AND GATE 7408
IC 7408
7408 AND fan in
7408 AND GATE fan in
74LS08P
propagation delay ic 74ls08
IC 7408 gate
74LS08
74LS08 fan in
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74ls786
Abstract: 74LS78 ic 74ls78
Text: 78 CO NNECTIO N DIAGRAMS PINOUT A ^ 4 H /7 4 H 7 8 £ V / - 5 Ö v/54LS/74LS78 6 1> c ~ / C5 DUAL JK FLIP-FLOP With Common Clear and Clock and Separate Set Inputs DESCRIPTION — The 'H78 is a dual JK master/slave flip -flo p with separate Direct Set inputs, a common Direct Clear input and a common C lock Pulse
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v/54LS/74LS78
54/74H
54/74LS
CLS78)
74ls786
74LS78
ic 74ls78
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