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    74LS138 FUNCTION TABLE Search Results

    74LS138 FUNCTION TABLE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    MHM411-21 Murata Manufacturing Co Ltd Ionizer Module, 100-120VAC-input, Negative Ion Visit Murata Manufacturing Co Ltd
    TCTH022AE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Push-pull type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH022BE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=10μA / IDD=11.3μA / Open-drain type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH012BE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Open-drain type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation
    TCTH012AE Toshiba Electronic Devices & Storage Corporation Over Temperature Detection IC / VDD=1.7~5.5V / IPTCO=1μA / IDD=1.8μA / Push-pull type / FLAG signal latch function Visit Toshiba Electronic Devices & Storage Corporation

    74LS138 FUNCTION TABLE Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    pin diagram of ic 74ls138

    Abstract: 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function 74LS138 LOGIC OF 74LS138 74LS138 3 to 8 decoder Pin pin for 74LS138 74ls138 3-8
    Text: 74LS138, S138 Signetics Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product Specification Logic Products FEATURES • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Direct replacement for Intel 3205 74LS138


    OCR Scan     		74LS138, 74LS138 74S138 N74S13BN, N74LS138N N74LS138D, N74S138D 1N916, 1N3064, 500ns pin diagram of ic 74ls138 74LS138 pin configuration ic 74ls138 74LS138 pin diagram 74ls138 function LOGIC OF 74LS138 74LS138 3 to 8 decoder Pin pin for 74LS138 74ls138 3-8 PDF

    LOGIC OF 74LS138

    Abstract: 74LS138 3 to 8 decoder notes 74LS138 pin configuration 74LS138 pin for 74LS138 74LS138 3 to 8 decoder Pin 74LS138 3 to pin configuration
    Text: Signetics 74LS138, S138 Decoders/Demultiplexers 1-Of-8 Decoder/Demultiplexer Product Specification Logic Products FEATURES • Multiple input enable for easy expansion • Ideal for memory chip select decoding • Direct replacement for Intel 3205 TYPICAL PROPAGATION


    OCR Scan     		74LS138, 74LS138 74S138 N74S138N, N74LS138N N74LS138D, N74S138D 1N916, 1N3064, 500ns LOGIC OF 74LS138 74LS138 3 to 8 decoder notes 74LS138 pin configuration pin for 74LS138 74LS138 3 to 8 decoder Pin 74LS138 3 to pin configuration PDF

    LOGIC OF 74LS138

    Abstract: pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder 74ls138 function TTL 74ls138 74LS138 3 to 8 decoder Pin
    Text: 74LS138, S138 Signetics Decoders/Dem ultiplexers 1-Of-8 D e co d e r/D e m u ltip le xe r Product Specification L o g ic P rod ucts FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory chip select decoding


    OCR Scan     		74LS138, 1-of-32 1N916, 1N3064, 500ns LOGIC OF 74LS138 pin for 74LS138 74LS138 3 to 8 decoder notes 74LS138 74LS138 pins 74l5138 of 74LS138 3 to 8 decoder 74ls138 function TTL 74ls138 74LS138 3 to 8 decoder Pin PDF

    74LS138

    Abstract: 74LS138 3 to 8 decoder Pin 74LS138 pin diagram ls138 74LS138 3 to 8 decoder notes pin for 74LS138 TTL 74ls138 Truth table of 1 to 16 demultiplexer of 74LS138 3 to 8 decoder 74ls138 truth table
    Text: SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32


    Original     		SN54/74LS138 74LS138 1-of-24 LS138 1-of-32 LS138s 74LS138 3 to 8 decoder Pin 74LS138 pin diagram 74LS138 3 to 8 decoder notes pin for 74LS138 TTL 74ls138 Truth table of 1 to 16 demultiplexer of 74LS138 3 to 8 decoder 74ls138 truth table PDF

    74ls138 truth table

    Abstract: 74LS138 74 LS 138 DECODER connection for 74LS138 74LS138 3 to 8 decoder Pin demultiplexer 3 to 8 truth table 74ls138 demultiplexer LS138 LOGIC OF 74LS138 of 74LS138 3 to 8 decoder
    Text: g MOTOROLA SN54/74LS138 1-0F-8 DECODER/ DEMULTIPLEXER The LSTTL/MSI SN54/74LS138 is a high speed 1-of-8 Decoder/ Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel ex­


    OCR Scan     		SN54/74LS138 1-of-24 LS138 1-of-32 LS138s SN54/74LS138 74ls138 truth table 74LS138 74 LS 138 DECODER connection for 74LS138 74LS138 3 to 8 decoder Pin demultiplexer 3 to 8 truth table 74ls138 demultiplexer LOGIC OF 74LS138 of 74LS138 3 to 8 decoder PDF

    Untitled

    Abstract: No abstract text available
    Text: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • • • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception Schottky Clamped for High Performance


    OCR Scan     		GD54/74LS138 PDF

    M02S7S7

    Abstract: No abstract text available
    Text: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature Pin Configuration • Designed Specifically for High Speed Memory Decoders and Data Transmission Systems • Incorporate 3 Enable Inputs to Simplify Cascading AND/OR Data Reception • Schottky Clamped for High Performance


    OCR Scan     		GD54/74LS138 Q004225 M02S7S7 PDF

    block diagram of 74LS138 3 to 8 decoder

    Abstract: block diagram of 74LS138 1 line to 16 line TTL 74ls138 74LS138 74LS138 3 to 8 74LS138 application note 74LS138 pin configuration 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74ls138 3-8
    Text: GD54/74LS138 3-TO-8-LINE DECODERS/DEMULTIPLEXERS Feature • Pin Configuration • D esigned Specifically for High S p e e d M em ory D ec o d e rs and Data Transm ission System s Incorporate 3 Enable Inputs to Simplify Cascading • A N D /O R Data R eception


    OCR Scan     		GD54/74LS138 block diagram of 74LS138 3 to 8 decoder block diagram of 74LS138 1 line to 16 line TTL 74ls138 74LS138 74LS138 3 to 8 74LS138 application note 74LS138 pin configuration 74LS138 3 to 8 decoder Pin of 74LS138 3 to 8 decoder 74ls138 3-8 PDF

    Untitled

    Abstract: No abstract text available
    Text: Am25LS138 • Am54LS/74LS138 3-Line To 8-Line Decoder/Demultiplexer D IS T IN C T IV E C H A R A C T E R IS T IC S L O G IC D IA G R A M • Inverting and non-inverting enable inputs • A m 2 5 L S devices offer the following improvements over Am 54/74LS


    OCR Scan     		Am25LS138 Am54LS/74LS138 54/74LS Am25LS/54 LS/74LS138 PDF

    intel 8085 microprocessor

    Abstract: 8085 memory organization 8085 microprocessor 74LS373 Decoder latch used for 8085 ic 74ls138 8085 clock circuit 8085 hardware reset 74LS138 decoder 8085 microprocessor application
    Text: Designing with the HDSP-211X Smart Display Family Application Note 1033 Introduction Hewlett-Packard’s smart alphanumeric display, the HDSP-211X, is built to optimize the user’s display design. Each HDSP-211X has an on-board CMOS IC which displays eight alphanumeric characters. The


    Original     		HDSP-211X HDSP-211X, intel 8085 microprocessor 8085 memory organization 8085 microprocessor 74LS373 Decoder latch used for 8085 ic 74ls138 8085 clock circuit 8085 hardware reset 74LS138 decoder 8085 microprocessor application PDF

    8085 microprocessor

    Abstract: intel 8085 microprocessor IC 74ls138 8085 memory organization 74LS373 Decoder 8085 microprocessor Datasheet 8085 microprocesor ic 74ls138 information interfacing of ram with 8085 intel 8085
    Text: Designing with the Avago Technologies HDSP-211x Smart Display Family Application Note 1033 Introduction Avago Technologies’ smart alphanumeric display, the HDSP-211x, is built to optimize the user’s display design. Each HDSP-211x has an on-board CMOS IC which


    Original     		HDSP-211x HDSP-211x, HDSP-211x 5988-5632EN 8085 microprocessor intel 8085 microprocessor IC 74ls138 8085 memory organization 74LS373 Decoder 8085 microprocessor Datasheet 8085 microprocesor ic 74ls138 information interfacing of ram with 8085 intel 8085 PDF

    74LS138 3 to 8 decoder notes

    Abstract: 74LS138 DATASHEET motorola 74ls138 TTL 74ls138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 data sheet 74LS138 1 to 8 decoder notes 74LS138 application note 74ls138 LS138 Motorola
    Text: SN54/74LS138 1-OF-8 DECODER/ DEMULTIPLEXER The LSTTL / MSI SN54 / 74LS138 is a high speed 1-of-8 Decoder / Demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three LS138 devices or to a 1-of-32


    Original     		SN54/74LS138 74LS138 1-of-24 LS138 1-of-32 LS138s 74LS138 3 to 8 decoder notes 74LS138 DATASHEET motorola 74ls138 TTL 74ls138 FUNCTIONAL APPLICATION OF 74LS138 74LS138 data sheet 74LS138 1 to 8 decoder notes 74LS138 application note LS138 Motorola PDF

    l381

    Abstract: and gate 74LS138 74ls138 function 74LS138 pin for 74LS138 74LS138 pin diagram SP74SC138F SP74SC138N pin diagram demultiplexer 74LS138
    Text: y SP74SC138 DECODER/DEMULTIPLEXER PIN CONFIGURATION A FEATURES B • Designed for high performance memory decoders in microprocessor systems ■ 3 to 8 line decoders include 3 enable inputs ■ Pin com patible with 74LS138 ■ SPI CMOS technology ■ Full TTL interface capability


    OCR Scan     		SP74SC138 74LS138 SP74SC138 74LS138. 400//A l381 and gate 74LS138 74ls138 function 74LS138 pin for 74LS138 74LS138 pin diagram SP74SC138F SP74SC138N pin diagram demultiplexer 74LS138 PDF

    64LS138

    Abstract: No abstract text available
    Text: S N 5 4 LS 13 8 , SN 54S138, S N 74 LS 13 8 , S N 74 S 13 8 A 3-LINE TO 8-LINE D EC OD ERS/DEM U LTIPLEXERS DECEMBER 1972 —REVISED MARCH 1988 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems I I 3 Enable Inputs to Simplify Cascading


    OCR Scan     		54S138, 64LS138 PDF

    SN54138

    Abstract: SN74LS138 LS138 SN54LS138 SN54S138 SN74S138A gl 1151
    Text: SN54LS138, SN54S138, SN74LS138, SN74S138A 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS D E C E M B E R 1972 — R E V IS E D M A R C H 1988 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems S N 54LS 138, S N 54S 138 SN 74LS 138, S N 74S 138A


    OCR Scan     		SN54LS13B, SN54S138, SN74LS138, SN74S138A 1972-REVISED usuall5012 SN74S138A sn54s138 SN54138 SN74LS138 LS138 SN54LS138 gl 1151 PDF

    ic 74ls138

    Abstract: 74LS138M 74LS139C N74LS139
    Text: TYPES SN54LS138. SN54LS139. SM54S13I, SNS4S139, SN74LS138. SM74LS139, SN74SB8. SN74S139 DECODERS/DEMULTIPLEXERS TTL MSI _ B U L L E T IN NO. DL-S 7611804, D E C E M B E R 1 9 7 2 -R E V IS E O O C T O B E R 1976 • Designed Specifically for High-Speed:


    OCR Scan     		SN54LS138. SN54LS139. SM54S13I, SNS4S139, SN74LS138. SM74LS139, SN74SB8. SN74S139 LS138 LS139 ic 74ls138 74LS138M 74LS139C N74LS139 PDF

    connection diagram of ic 74ls138

    Abstract: pin diagram of ic 74ls138 pin for 74LS138 74ls138 function sn54ls138 SN54LS13B 74LS138 function table ic 74ls138 74ls138 74S138A
    Text: SN54LS13B, SN54S138, SN74LS138, SN74S13BA 3 LINE TO 8 UNE DECODERSjDEMULTIPLEXERS DECEMBER 1 9 7 2 -R E V IS E D M AR C H 1 9 8 8 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems SN 5 4 LS 1 38 , S N 54S 138 . . . J OR W PACKAG E


    OCR Scan     		SN54LS13B, SN54S138, SN74LS138, SN74S13BA 74LS138, 74S138A SN74S138A 54S138 74S138A connection diagram of ic 74ls138 pin diagram of ic 74ls138 pin for 74LS138 74ls138 function sn54ls138 SN54LS13B 74LS138 function table ic 74ls138 74ls138 PDF

    and gate 74LS138

    Abstract: M54HCT138 M74HCT138 74ls138 truth table
    Text: M54HCT138 M74HCT138 HS-CMOS o a , « INTEGRATED CIRCUITS 4 PR O D U C T PR EVIEW 3 TO 8 LINE DECODER DESCRIPTION The M 54/74H C T 138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. It has the same high speed perform ance of LSTTL


    OCR Scan     		M54HCT138 M74HCT138 M54/74HCT138 and gate 74LS138 M74HCT138 74ls138 truth table PDF

    IC 74LS138

    Abstract: connection diagram of ic 74ls138 74s138 SNS4LS138 SN74S138
    Text: TYPES SNS4LS138, SN54S138, SN74LS138, SN74S138 3-LiNE TO 8-LINE DECODERS/DEMULTIPLEXERS D E C E M B E R 1 9 7 2 - R E V I S E D A P R IL 1 9 8 5 Designed Specifically for High-Speed: Memory Decoders Data Transmission Systems S N 5 4 L S 1 3 8 . S N 5 4 S 1 3 8 . . . J OR W P A C K A G E


    OCR Scan     		SNS4LS138, SN54S138, SN74LS138, SN74S138 54S138 74S138 IC 74LS138 connection diagram of ic 74ls138 SNS4LS138 PDF

    74LS138 pin diagram

    Abstract: ASTAS MD74HCT138RE 74HCT138 74ls138 MD54HCT138 Hll logic 74HCT138 DIP
    Text: mm ' MQ54/MHCÎÎ38R 1 o f 8 O e U l t ^ o ^ / O ç n j ^ ^ if er Features CONNECTION DIAG RAM OU> TOP VIEW • High latch-up immunity • High current outputs can drive 15 LSTTL loads ? . ’ • Low power ISO-CMOS technology A. -C 1 A, C 2 A2 t 3 • Meets or exceeds all proposed JEDEC 40.2


    OCR Scan     		54/74LS138 MD54/74HCT138 MD54HÃ T138RC, MD74HCT138RE, 74LS138 pin diagram ASTAS MD74HCT138RE 74HCT138 74ls138 MD54HCT138 Hll logic 74HCT138 DIP PDF

    of 74LS138 3 to 8 decoder

    Abstract: MD74HCT138
    Text: wmmwttw 1 of a Ocial D *m >d«/P!«n^i|p^ar Features CONNECTION DIAGRAM OH> TOP VIEW • High latch-up immunity • High current outputs can drive 15 LSTTL loads V C 1 • Low power ISO -C M O S technology A, c 2 16 3 V « '5 a, : 3 14 , c 4 i . ’ • Meets or exceeds all proposed JEDEC 40.2


    OCR Scan     		54/74LS138 MD54/74HCT138 MD54H T138RC, MD74HCT138RE, of 74LS138 3 to 8 decoder MD74HCT138 PDF

    74LS80

    Abstract: 74LS198 74LS150 74LS94 OAI32 74LS179 TTL 74LS198 MUX21H TTL 74ls138 to 7 segment 7476 3 bit ripple counter
    Text: 4flE ]> • 77MLjbciO 0001L3M 4bO « P C H T- °J EK-044-9004 CMOS Gate Array 5GV Series RICOH CORP/ ELECTRONIC The RICOH gate array 5GV series complies with the CMOS 1.5ju rule, and offers high speed operation with a gate delay time of 1.0 ns. The 5GV series inherits the rich library of 5GF gate array series. The cell library is compatible with


    OCR Scan     		77MLjbc 0001L3M TEK-044-9004 RSC-15 TBF368 M390C M393C CM16BR* M540C M541C 74LS80 74LS198 74LS150 74LS94 OAI32 74LS179 TTL 74LS198 MUX21H TTL 74ls138 to 7 segment 7476 3 bit ripple counter PDF

    74LS138PC

    Abstract: No abstract text available
    Text: 138 CONNECTION DIAGRAM PINOUT A & 54S/74S138 54LS/74LS138 bi f rC 1-0F-8 DECODER/DEMULTIPLEXER D E S C R IP TIO N — The '138 is a high speed 1-of-8 decoder/dem ultiplexer. This device is ideally suited for high speed bipolar memory chip select ad­ dress decoding. The m ultiple input enables allow parallel expansion to a


    OCR Scan     		54S/74S138 54LS/74LS138 1-Of-24 1-of-32 74LS138PC PDF

    8085 microprocessor pin diagram

    Abstract: interfacing 8085 with lcd 8085 microprocessor 8085 microprocessor Datasheet z80 9 digit 7 segment display code MICROPROCESSOR Z80 7segment 6502 timing diagram z80 9 digit 7 segment display 6502 microprocessor 4 digit 7 segment lcd display pin configuration
    Text: APPLICATION NOTE 19 TC7211AM DISPLAY DRIVER MICROPROCESSOR INTERFACE TC7211AM DISPLAY DRIVER MICROPROCESSOR INTERFACE By Wes AN-19 Freeman MICROPROCESSOR INTERFACING MICROPROCESSOR BUS INTERFACES The TC7211AM is a complete CMOS 4-digit display driver that greatly simplifies microprocessor display interfacing. This device contains data latches, BCD to 7-segment decoders, and backplane and segment drivers for


    Original     		TC7211AM AN-19 6800-type, 8080-type, 8085 microprocessor pin diagram interfacing 8085 with lcd 8085 microprocessor 8085 microprocessor Datasheet z80 9 digit 7 segment display code MICROPROCESSOR Z80 7segment 6502 timing diagram z80 9 digit 7 segment display 6502 microprocessor 4 digit 7 segment lcd display pin configuration PDF