AN6081
Abstract: No abstract text available
Text: Migration to 90 nm 5V Async SRAMs AN6081 Abstract This application note is to help users of Cypress 5V asynchronous SRAMs Fast Async and Micropower SRAMs product family migrate from existing technology to the latest 90 nm technology. Introduction Cypress started qualifying its state-of-the-art 90 nm technology asynchronous SRAMs in early 2006. These products,
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AN6081
AN6081
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ispClock5406
Abstract: AN6081 SG-710ECK ispClock5400 SG-71 ispCLOCK5406D
Text: Driving SERDES Devices with the ispClock5400D Differential Clock Buffer October 2009 Application Note AN6081 Introduction In this application note we focus on how the ispClock 5406D and a low-cost CMOS oscillator can be utilized to drive the reference clock for SERDES-based applications. SERDES applications require accurate and low-jitter
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ispClock5400D
AN6081
ispClockTM5406D
ispClock5406D
1-800-LATTICE
ispClock5406
AN6081
SG-710ECK
ispClock5400
SG-71
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Untitled
Abstract: No abstract text available
Text: CY7C109D CY7C1009D 1-Mbit 128 K x 8 Static RAM 1-Mbit (128 K × 8) Static RAM Features • Pin- and function-compatible with CY7C109B/CY7C1009B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA
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CY7C109D
CY7C1009D
CY7C109B/CY7C1009B
CY7C109D
32-pin
400-Mil
CY7C1009D
300-Mil
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Untitled
Abstract: No abstract text available
Text: CY62128E MoBL 1-Mbit 128 K x 8 Static RAM 1-Mbit (128 K × 8) Static RAM Features Functional Description • Very high speed: 45 ns The CY62128E is a high performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This
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CY62128E
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Untitled
Abstract: No abstract text available
Text: CY62138F MoBL 2-Mbit 256 K x 8 Static RAM 2-Mbit (256 K × 8) Static RAM Features Functional Description • High speed: 45 ns The CY62138F is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This
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CY62138F
CY62138V
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Untitled
Abstract: No abstract text available
Text: CY62146E MoBL 4-Mbit 256 K x 16 Static RAM 4-Mbit (256 K × 16) Static RAM Features feature that reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE
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CY62146E
I/O15)
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Untitled
Abstract: No abstract text available
Text: CY7C1011CV33-10BAJXET Alert me about changes to this product Status: In Production Datasheet Inventory Packaging/Ordering Quality and RoHS Technical Documents Related Products Support and Community CY7C1011CV33-10BAJXET Automotive Qualified Y Min. Operating Voltage V
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CY7C1011CV33-10BAJXET
AN6081
90-nm
CY7C1011CV33-10BAJXET
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Untitled
Abstract: No abstract text available
Text: CY7C10212CV33-12BAXET Alert me about changes to this product Status: In Production Datasheet Inventory Packaging/Ordering Quality and RoHS Technical Documents Related Products Support and Community CY7C10212CV33-12BAXET Automotive Qualified Y Min. Operating Voltage V
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CY7C10212CV33-12BAXET
10Last
AN6081
90-nm
PIN135200
CY7C10212CV33-12BAXET
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Untitled
Abstract: No abstract text available
Text: CY62128E MoBL 1-Mbit 128 K x 8 Static RAM 1-Mbit (128 K × 8) Static RAM Features Functional Description • Very high speed: 45 ns The CY62128E is a high performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This
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CY62128E
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Abstract: No abstract text available
Text: CY62157ESL MoBL 8-Mbit 512 K x 16 Static RAM 8-Mbit (512 K × 16) Static RAM Features • Very high speed: 45 ns ■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V ■ Ultra low standby power ❐ Typical Standby current: 2 A ❐ Maximum Standby current: 8 A
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CY62157ESL
44-pin
I/O15)
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81134A
Abstract: an-596 hyperlynx 60810 AN608 Touchstone Semiconductor
Text: AN 608: HST Jitter and BER Estimator Tool for Stratix IV GX and GT Devices July 2010 AN-608-1.0 The high-speed communication link design toolkit HST jitter and bit error rate (BER) estimator tool is a statistical behavior model-based simulation tool that estimates the
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AN-608-1
81134A
an-596
hyperlynx
60810
AN608
Touchstone Semiconductor
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HW-USBN-2A Schematic
Abstract: D1N4448 smd diode 95e jtag cable lattice Schematic hw-dln-3c ispCLOCK5406D HW-USBN-2A AN6081 R17 SMA HW-usb smd 4n
Text: ispClock5400D Evaluation Board User’s Guide December 2009 Revision: EB50_01.1 ispClock5400D Evaluation Board User’s Guide Lattice Semiconductor Introduction Thank you for choosing the Lattice Semiconductor ispClock device family! This guide describes how to start using the ispClock5400D Evaluation Board, an easy-to-use platform for evaluating and designing with the ispClock5406D in-system-programmable differential clock distribution device. The evaluation board can be used stand-alone to review the performance and in-system programmability of the
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ispClock5400D
ispClock5406D
EVQ-QXT03W
OT-23
MMBT2369A
OT-223
HW-USBN-2A Schematic
D1N4448
smd diode 95e
jtag cable lattice Schematic hw-dln-3c
HW-USBN-2A
AN6081
R17 SMA
HW-usb
smd 4n
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Untitled
Abstract: No abstract text available
Text: CY62167E MoBL 16-Mbit 1 M x 16 / 2 M × 8 Static RAM 16-Mbit (1 M × 16 / 2 M × 8) Static RAM Features • Configurable as 1 M × 16 or as 2 M × 8 SRAM ■ Very high speed: 45 ns ■ Wide voltage range: 4.5 V to 5.5 V ■ Ultra low standby power ❐ Typical standby current: 1.5 µA
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CY62167E
16-Mbit
I/O15)
48-pin
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Untitled
Abstract: No abstract text available
Text: CY7C1049D 4-Mbit 512 K x 8 Static RAM 4-Mbit (512 K × 8) Static RAM Features provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable
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CY7C1049D
CY7C1049B
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cy7c1019d
Abstract: No abstract text available
Text: CY7C1019D 1-Mbit 128 K x 8 Static RAM 1-Mbit (128 K × 8) Static RAM Features Functional Description The CY7C1019D [1] is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW
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CY7C1019D
CY7C1019B
cy7c1019d
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Untitled
Abstract: No abstract text available
Text: CY62136ESL MoBL 2-Mbit 128 K x 16 Static RAM 2-Mbit (128 K × 16) Static RAM Features • Very high speed: 45 ns ■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 7 A
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CY62136ESL
I/O15)
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Untitled
Abstract: No abstract text available
Text: CY7C1011CV33-10BAJXE Alert me about changes to this product Status: In Production Datasheet Inventory Packaging/Ordering Quality and RoHS Technical Documents Related Products Support and Community CY7C1011CV33-10BAJXE Automotive Qualified Y Min. Operating Voltage V
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CY7C1011CV33-10BAJXE
AN6081
90-nm
CY7C1011CV33-10BAJXE
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Untitled
Abstract: No abstract text available
Text: CY7C199D-25SXE Alert me about changes to this product Status: In Production Datasheet Inventory Packaging/Ordering Quality and RoHS Technical Documents Related Products Support and Community CY7C199D-25SXE Automotive Qualified Y Min. Operating Voltage V
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CY7C199D-25SXE
100-BLY
AN6081
90-nm
CY7C199D-25SXE
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D1N4448
Abstract: jtag cable lattice Schematic hw-dln-3c schematic ispDOWNLOAD Cable lattice hw-dln-3c HW-DLN-3C HW-USBN-2A Schematic HW-USBN-2A AN6081 circuit ispDOWNLOAD Cable lattice hw-dln-3c FzT649TA ispDOWNLOAD Cable lattice hw-dln-3c
Text: ispClock5400D Evaluation Board User’s Guide July 2010 Revision: EB50_01.2 ispClock5400D Evaluation Board User’s Guide Lattice Semiconductor Introduction Thank you for choosing the Lattice Semiconductor ispClock device family! This guide describes how to start using the ispClock5400D Evaluation Board, an easy-to-use platform for evaluating and designing with the ispClock5406D in-system-programmable differential clock distribution device. The evaluation board can be used stand-alone to review the performance and in-system programmability of the
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ispClock5400D
ispClock5406D
EVQ-QXT03W
OT-23
MMBT2369A
OT-223
D1N4448
jtag cable lattice Schematic hw-dln-3c
schematic ispDOWNLOAD Cable lattice hw-dln-3c
HW-DLN-3C
HW-USBN-2A Schematic
HW-USBN-2A
AN6081
circuit ispDOWNLOAD Cable lattice hw-dln-3c
FzT649TA
ispDOWNLOAD Cable lattice hw-dln-3c
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Untitled
Abstract: No abstract text available
Text: CY7C199D 256-Kbit 32 K x 8 Static RAM 256-Kbit (32 K × 8) Static RAM Features Functional Description • Temperature range ❐ –40 °C to 85 °C The CY7C199D is a high performance CMOS static RAM organized as 32,768 words by 8-bits. Easy memory expansion is
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CY7C199D
256-Kbit
CY7C199D
CY7C199C
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Untitled
Abstract: No abstract text available
Text: CY62158E MoBL 8-Mbit 1 M x 8 Static RAM 8-Mbit (1 M × 8) Static RAM Features • Very high speed: 45 ns ❐ Wide voltage range: 4.5 V–5.5 V applications. The device also has an automatic power down feature that significantly reduces power consumption. Placing
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CY62158E
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Untitled
Abstract: No abstract text available
Text: CY62126ESL MoBL 1-Mbit 64 K x 16 Static RAM 1-Mbit (64 K × 16) Static RAM Features addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The input and output pins (I/O0
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CY62126ESL
I/O15)
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Untitled
Abstract: No abstract text available
Text: CY62157E MoBL 8-Mbit 512 K x 16 Static RAM 8-Mbit (512 K × 16) Static RAM Features addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input or output pins (I/O0 through I/O15) are
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CY62157E
I/O15)
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Untitled
Abstract: No abstract text available
Text: CY7C1019D 1-Mbit 128 K x 8 Static RAM 1-Mbit (128 K × 8) Static RAM Features Functional Description The CY7C1019D [1] is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW
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CY7C1019D
CY7C1019B
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