CY7C1270V18 Search Results

CY7C1270V18 Price and Stock

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Infineon Technologies AG CY7C1270V18-375BZI IC SRAM 36MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1270V18-375BZI	Tray			105	1 - 10 - 100 - 1000 $57.08581 10000 $57.08581	Buy Now
Infineon Technologies AG CY7C1270V18-400BZC IC SRAM 36MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1270V18-400BZC	Tray			105	1 - 10 - 100 - 1000 $54.60962 10000 $54.60962	Buy Now
Infineon Technologies AG CY7C1270V18-375BZC IC SRAM 36MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1270V18-375BZC	Tray			105	1 - 10 - 100 - 1000 $56.18038 10000 $56.18038	Buy Now
Rochester Electronics LLC CY7C1270V18-400BZXC IC SRAM 36MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1270V18-400BZXC	Tray			6	1 - 10 $51.64 100 $51.64 1000 $51.64 10000 $51.64	Buy Now
Infineon Technologies AG CY7C1270V18-400BZXC IC SRAM 36MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1270V18-400BZXC	Tray			105	1 - 10 - 100 - 1000 $54.60962 10000 $54.60962	Buy Now

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CY7C1270V18 Datasheets (6)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1270V18		Cypress Semiconductor	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)		Original	PDF
CY7C1270V18-375BZC		Cypress Semiconductor	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)		Original	PDF
CY7C1270V18-375BZI		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 36MBIT 375MHZ 165FBGA		Original	PDF
CY7C1270V18-375BZXC		Cypress Semiconductor	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)		Original	PDF
CY7C1270V18-400BZC		Cypress Semiconductor	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)		Original	PDF
CY7C1270V18-400BZXC		Cypress Semiconductor	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)		Original	PDF

CY7C1270V18 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
Untitled Abstract: No abstract text available Text: CY7C1268V18 CY7C1270V18 PRELIMINARY 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • • • • 36-Mbit density (2M x 18, 1M x 36) 300 MHz to 400 MHz clock for high bandwidth 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1268V18 CY7C1270V18 36-Mbit 165-bas
Untitled Abstract: No abstract text available Text: CY7C1266V18 CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • • • • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1266V18 CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit
Untitled Abstract: No abstract text available Text: THIS SPEC IS OBSOLETE Spec No: 001-06347 Spec Title: CY7C1266V18/CY7C1277V18/CY7C1268V18/ CY7C1270V18, 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Sunset Owner: Jayasree Nayar (NJY) Replaced by: None CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18	Original	PDF	CY7C1266V18/CY7C1277V18/CY7C1268V18/ CY7C1270V18, 36-Mbit CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18
tms 980 Abstract: No abstract text available Text: CY7C1277V18 CY7C1268V18 CY7C1270V18 PRELIMINARY 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 36-Mbit density (4M x 9, 2M x 18, 1M x 36) • 300 MHz to 400 MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	PDF	CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit CY7C1277V18/CY7C1268V18/CY7C1270V18 tms 980
CY7C1266V18 Abstract: CY7C1268V18 CY7C1270V18 CY7C1277V18 Text: CY7C1266V18 CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • • • • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1266V18 CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit CY7C1266V18, CY7C1277V18, CY7C1268V18, CY7C1270V18 CY7C1266V18 CY7C1268V18 CY7C1277V18
CY7C1266V18 Abstract: CY7C1268V18 CY7C1270V18 CY7C1277V18 Text: CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) ■ 300 MHz to 400 MHz clock for high bandwidth	Original	PDF	CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 36-Mbit CY7C1277V18, CY7C1270V18 CY7C1266V18 CY7C1268V18 CY7C1277V18