CY7C1303BV25 Search Results

CY7C1303BV25 Price and Stock

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Rochester Electronics LLC CY7C1303BV25-167BZC IC SRAM 18MBIT PAR 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1303BV25-167BZC	Tray			12	1 - 10 - 100 $25.43 1000 $25.43 10000 $25.43	Buy Now
Infineon Technologies AG CY7C1303BV25-167BZC IC SRAM 18MBIT PAR 165FBGA
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DigiKey	CY7C1303BV25-167BZC	Tray				1 - 10 - 100 - 1000 - 10000 -	Buy Now
Verical	CY7C1303BV25-167BZC		59		1	1 $17.6 10 $17.6 100 $17.6 1000 $17.6 10000 $17.6	Buy Now
Arrow Electronics	CY7C1303BV25-167BZC		59		1	1 $17.6 10 $17.6 100 $17.6 1000 $17.6 10000 $17.6	Buy Now
Cypress Semiconductor CY7C1303BV25-167BZC SRAM Chip Sync Dual 2.5V 18M-bit 1M x 18 2.5ns 165-Pin FBGA Tray
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical	CY7C1303BV25-167BZC		335		13	1 - 10 - 100 $28.725 1000 $25.975 10000 $25.975	Buy Now
	CY7C1303BV25-167BZC		67		13	1 - 10 - 100 $28.725 1000 $25.975 10000 $25.975	Buy Now
	CY7C1303BV25-167BZC		57		13	1 - 10 - 100 $28.725 1000 $25.975 10000 $25.975	Buy Now
Rochester Electronics	CY7C1303BV25-167BZC		554		1	1 $24.45 10 $24.45 100 $22.98 1000 $20.78 10000 $20.78	Buy Now

CY7C1303BV25 Datasheets (4)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1303BV25		Cypress Semiconductor	18-Mbit Burst of 2 Pipelined SRAM with QD Architecture		Original	PDF
CY7C1303BV25-100BZXC		Cypress Semiconductor	18-Mbit Burst of 2 Pipelined SRAM with QD Architecture		Original	PDF
CY7C1303BV25-167BZC		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 167MHZ 165FBGA		Original	PDF
CY7C1303BV25-167BZC		Cypress Semiconductor	18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture		Original	PDF

CY7C1303BV25 Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
CY7C1303BV25 Abstract: CY7C1306BV25 Text: CY7C1303BV25 CY7C1306BV25 PRELIMINARY 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	PDF	CY7C1303BV25 CY7C1306BV25 18-Mbit 167-MHz CY7C1303BV25/CY7C1306BV25 CY7C1303BV25 CY7C1306BV25
3M Touch Systems Abstract: No abstract text available Text: CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■	Original	PDF	CY7C1303BV25 18-Mbit CY7C1303BV25 3M Touch Systems
CY7C1303BV25 Abstract: CY7C1306BV25 Text: CY7C1303BV25 CY7C1306BV25 18 Mbit Burst of Two Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports ❐ Supports concurrent transactions ■ 167 MHz Clock for high bandwidth ❐ 2.5 ns Clock-to-Valid access time	Original	PDF	CY7C1303BV25 CY7C1306BV25 CY7C1303BV25 CY7C1306BV25
CY7C1303BV25 Abstract: CY7C1306BV25 Text: CY7C1303BV25 CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	PDF	CY7C1303BV25 CY7C1306BV25 18-Mbit 167-MHz CY7C1303BV25 CY7C1306BV25
CY7C1303BV25 Abstract: CY7C1306BV25 Text: CY7C1303BV25 CY7C1306BV25 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz Clock for high bandwidth — 2.5 ns Clock-to-Valid access time	Original	PDF	CY7C1303BV25 CY7C1306BV25 18-Mbit 167-MHz CY7C1303BV25 CY7C1306BV25
Untitled Abstract: No abstract text available Text: CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■	Original	PDF	CY7C1303BV25 18-Mbit
3M Touch Systems Abstract: No abstract text available Text: CY7C1303BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■	Original	PDF	CY7C1303BV25 18-Mbit CY7C1303BV25 3M Touch Systems
CY7C1303BV25 Abstract: CY7C1306BV25 3M Touch Systems Text: CY7C1303BV25 CY7C1306BV25 18-Mbit Burst of Two-Pipelined SRAM with QDR Architecture 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions	Original	PDF	CY7C1303BV25 CY7C1306BV25 18-Mbit CY7C1303BV25 CY7C1306BV25 3M Touch Systems
BV25 Abstract: CY7C129 CY7C130 CY7C131 CY7C132 EV25 ev18 Text: CY7C129DV18/CY7C130DV25 CY7C130BV18/CY7C130BV25/CY7C132BV25 CY7C131BV18 / CY7C132BV18/CY7C139BV18 CY7C191BV18/CY7C141AV18 / CY7C142AV18/ CY7C151V18 /CY7C152V18 Errata Revision: D March 04, 2008 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII, the Output Buffer, the JTAG and the DLL issue for	Original	PDF	CY7C129 DV18/CY7C130 CY7C130 BV18/CY7C130 BV25/CY7C132 CY7C131 CY7C132 BV18/CY7C139 CY7C191 BV18/CY7C141 BV25 EV25 ev18
CY7C1338-100AXC Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12	Original	PDF	CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
05564 Abstract: BV25 CY7C129 CY7C130 CY7C131 CY7C132 CY7C1422AV18 1428A Text: CY7C129DV18/CY7C130DV25 CY7C130BV18/CY7C130BV25/CY7C132BV25 CY7C131BV18 / CY7C132BV18/CY7C139BV18 CY7C191BV18/CY7C141AV18 / CY7C142AV18/ CY7C151V18 /CY7C152V18 Errata Revision: C May 02, 2007 RAM9 QDR-I/DDR-I/QDR-II/DDR- II Errata This document describes the DOFF issue for QDRII/DDRII and the Output Buffer and JTAG issues for	Original	PDF	CY7C129 DV18/CY7C130 CY7C130 BV18/CY7C130 BV25/CY7C132 CY7C131 CY7C132 BV18/CY7C139 CY7C191 BV18/CY7C141 05564 BV25 CY7C1422AV18 1428A