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    Untitled

    Abstract: No abstract text available
    Text: CY7C13101KV18, CY7C13251KV18 CY7C13121KV18, CY7C13141KV18 18-Mbit QDR II SRAM 2-Word Burst Architecture 18-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions


    Original     		18-Mbit CY7C13101KV18, CY7C13251KV18 CY7C13121KV18, CY7C13141KV18 CY7C13101KV18 CY7C13251KV18 CY7C13121KV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C13101KV18, CY7C13251KV18 CY7C13121KV18, CY7C13141KV18 18-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions CY7C13101KV18 – 2M x 8 ■ 333 MHz clock for high bandwidth


    Original     		18-Mbit CY7C13101KV18, CY7C13251KV18 CY7C13121KV18, CY7C13141KV18 CY7C13101KV18 CY7C13251KV18 CY7C13121KV18 PDF