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    CY7C1418JV18 Price and Stock

    Infineon Technologies AG CY7C1418JV18-300BZC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1418JV18-300BZC Tray
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    Rochester Electronics LLC CY7C1418JV18-300BZC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1418JV18-300BZC Tray 6
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    • 100 $58.4
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    Infineon Technologies AG CY7C1418JV18-300BZXC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1418JV18-300BZXC Tray
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    Rochester Electronics LLC CY7C1418JV18-300BZXC

    IC SRAM 36MBIT PARALLEL 165FBGA
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    DigiKey CY7C1418JV18-300BZXC Tray 6
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    • 100 $58.4
    • 1000 $58.4
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    Cypress Semiconductor CY7C1418JV18-300BZXC

    CY7C1418JV18-300BZXC
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    Verical CY7C1418JV18-300BZXC 1,530 6
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    • 1000 $59.6625
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    CY7C1418JV18-300BZXC 105 6
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    • 100 $65.975
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    CY7C1418JV18-300BZXC 105 6
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    CY7C1418JV18-300BZXC 17 6
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    Rochester Electronics CY7C1418JV18-300BZXC 1,862 1
    • 1 $56.15
    • 10 $56.15
    • 100 $52.78
    • 1000 $47.73
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    CY7C1418JV18 Datasheets (3)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1418JV18 Cypress Semiconductor 36-Mbit DDR-II SRAM 2-Word Burst Architecture Original PDF
    CY7C1418JV18-300BZC Cypress Semiconductor 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V Original PDF
    CY7C1418JV18-300BZXC Cypress Semiconductor 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V Original PDF

    CY7C1418JV18 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CY7C1416JV18

    Abstract: CY7C1418JV18 CY7C1420JV18 CY7C1427JV18 MAX9930
    Text: CY7C1416JV18, CY7C1427JV18 CY7C1418JV18, CY7C1420JV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original
    PDF CY7C1416JV18, CY7C1427JV18 CY7C1418JV18, CY7C1420JV18 36-Mbit CY7C1416JV18 CY7C1418JV18 CY7C1420JV18 CY7C1427JV18 MAX9930

    Untitled

    Abstract: No abstract text available
    Text: CY7C1418JV18 CY7C1420JV18 36-Mbit DDR II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces


    Original
    PDF CY7C1418JV18 CY7C1420JV18 36-Mbit CY7C1420JV18 CY7C1420JV18, 18-bit

    Untitled

    Abstract: No abstract text available
    Text: CY7C1416JV18, CY7C1427JV18 CY7C1418JV18, CY7C1420JV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original
    PDF CY7C1416JV18, CY7C1427JV18 CY7C1418JV18, CY7C1420JV18 36-Mbit CY7C1427JV18, CY7C1418JV18 CY7C1420JV18 CY7C1416JV18

    CY7C1416JV18

    Abstract: CY7C1418JV18 CY7C1420JV18 CY7C1427JV18
    Text: CY7C1416JV18, CY7C1427JV18 CY7C1418JV18, CY7C1420JV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency


    Original
    PDF CY7C1416JV18, CY7C1427JV18 CY7C1418JV18, CY7C1420JV18 36-Mbit CY7C1416JV18 CY7C1418JV18 CY7C1420JV18 CY7C1427JV18