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Catalog Datasheet	MFG & Type	PDF	Document Tags
48-PIN Abstract: CDC318A CDC318ADL CDC318ADLG4 Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A CDC318ADL CDC318ADLG4
48-PIN Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A 18LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR
K3638 Abstract: 4Y04 Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin K3638 4Y04
48-PIN Abstract: CDC318A Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A 18LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A
k3638 Abstract: No abstract text available Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin k3638
Untitled Abstract: No abstract text available Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin
CDC318A Abstract: No abstract text available Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614 – SEPTEMBER 1998 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps	Original	PDF	CDC318A 18-LINE SCAS614 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A
48-PIN Abstract: CDC318A Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A
48-PIN Abstract: CDC318A Text: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A
Untitled Abstract: No abstract text available Text: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	PDF	CDC318A 18LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin