32-PIN
Abstract: SST30VR041 SST30VR043 SST31LF041A cl381
Text: 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Preliminary Specifications SST30VR041/0434 Mb Mask ROM x8 + 1 Mb / 256 Kbit SRAM (x8) Combo FEATURES: • ROM + SRAM ROM/RAM Combo – SST30VR041: 512K x8 ROM + 128K x8 SRAM – SST30VR043: 512K x8 ROM + 32K x8 SRAM
|
Original
|
SST30VR041
SST30VR043
SST30VR041/0434
SST30VR041:
SST30VR043:
SST31LF041A
SST30VR043
32-pin
MO-142
cl381
|
PDF
|
SST30VR041
Abstract: SST30VR043 SST31LF041A 128k x8 SRAM TSOP
Text: 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet SST30VR041 / 0434Mb Mask ROM x8 + 1Mb / 256Kb SRAM (x8) Combo FEATURES: • Low Power Dissipation: – Standby: 1.0 µW (Typical) – Operating: 3.0 mW (Typical) • Fully Static Operation
|
Original
|
SST30VR041
SST30VR043
0434Mb
256Kb
32-lead
x14mm)
SST30VR041:
SST30VR043:
SST31LF041A
SST30VR043
128k x8 SRAM TSOP
|
PDF
|
TN218a
Abstract: tn218a.zip
Text: TN218a Implementing a Serial Download Manager for a 256K Byte Flash For Dynamic C version 7.31 and Later Disclaimer The programs described in this note are provided as a sample only with no guarantees that they are fail-safe. How fail-safe a system needs to be is obviously application dependent. It is
|
Original
|
TN218a
03D7B803D7E80FFFF3DF3EE00000000003DF39000
3D1830
00000001FF
TN218a
tn218a.zip
|
PDF
|
k 1358
Abstract: 56FBGA
Text: 32 Mbit Burst Mode Concurrent SuperFlash ComboMemory SST34WA32A3 / SST34WA32A4 / SST34WA3283 / SST34WA3284 Advance Information FEATURES: • Flash Organization: – 2M x 16 • PSRAM Organization: – 8 Mbit: 512k X 16 – 16 Mbit: 1M x 16 • Single Voltage Read and Write Operations
|
Original
|
SST34WA32A3
SST34WA32A4
SST34WA3283
SST34WA3284
SST34WA32x3
SST34WA32x4
MO-225,
56-fbga-MVN-6x8-1
56-Ball
S71358-01-000
k 1358
56FBGA
|
PDF
|
TP24-TP28
Abstract: A19N CY1352 33pF50V CER-0805
Text: 5 4 3 2 1 Mezzanine Connections pages 4-5 CT_C8_A CT_C8_B CT_FRAME_A CT_FRAME_B CT_D[31:0] CT_NETREF1 CT_NETREF2 CT_MC MC_CLOCK MC_RX MC_TX CT_C16_NEGATIVE CT_C16_POSITIVE CT_FR_COMP CT_C2 CT_C4 CT_SCLK CT_SCLKX2 General (pages 2-3) MTPLL_PRI MTPLL_SEC MTPLL_LOS1
|
Original
|
MT9044
TCLRMTPLLC43
EPF10K50E
MT90503
TP24-TP28
A19N
CY1352
33pF50V
CER-0805
|
PDF
|
CPU-A13
Abstract: R32237 10uf,16v 10uf16v CTD12 CER-0805
Text: 5 4 3 2 1 Mezzanine Connections TXA_CLK TXA_SOC TXA_PAR TXA_ENBTXA_CLAV TXA_DATA[7:0] General MTPLL_FS1 MTPLL_FS2 MTPLL_TCLRMTPLL_RSTMTPLL_RSEL MTPLL_LOS1 MTPLL_LOS2 MTPLL_MS1 MTPLL_MS2 MTPLL_PRI MTPLL_SEC D RXA_CLK RXB_CLK RXC_CLK TXA_CLK TXB_CLK TXC_CLK
|
Original
|
MT9044
MT9042
16OMT9044
32MHZ
CPU-A13
R32237
10uf,16v
10uf16v
CTD12
CER-0805
|
PDF
|
Untitled
Abstract: No abstract text available
Text: IN AR Y VS23S010C Datasheet VS23S010C-L - 1 Megabit SPI SRAM with Serial and Parallel Interfaces and Integrated Video Display Controller Features Description • Flexible 1.5V - 3.6V operating voltage • 131,072 x 8-bit SRAM organization • Serial Peripheral Interface SPI mode
|
Original
|
VS23S010C
VS23S010C-L
VS23S010C-L:
VS23S010A
FI-33720
|
PDF
|
TN218
Abstract: BIOS example delay source code
Text: TN218 Implementing a Serial Download Manager for a 256K Byte Flash For Dynamic C version 7.21 only Disclaimer The programs described in this note are provided as a sample only with no guarantees that they are fail-safe. How fail-safe a system needs to be is obviously application dependent. It is
|
Original
|
TN218
3D1830
00000001FF
TN218
BIOS example delay source code
|
PDF
|
SST30VR041
Abstract: SST30VR043 SST31LF041A
Text: 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet SST30VR041 / 0434Mb Mask ROM x8 + 1Mb / 256Kb SRAM (x8) Combo FEATURES: • ROM + SRAM ROM/RAM Combo – SST30VR041: 512K x8 ROM + 128K x8 SRAM – SST30VR043: 512K x8 ROM + 32K x8 SRAM
|
Original
|
SST30VR041
SST30VR043
0434Mb
256Kb
SST30VR041:
SST30VR043:
SST31LF041A
SST30VR043
|
PDF
|
Untitled
Abstract: No abstract text available
Text: 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet SST30VR041 / 0434Mb Mask ROM x8 + 1Mb / 256Kb SRAM (x8) Combo FEATURES: • Low Power Dissipation: – Standby: 1.0 µW (Typical) – Operating: 3.0 mW (Typical) • Fully Static Operation
|
Original
|
SST30VR041
SST30VR043
0434Mb
256Kb
SST30VR041:
SST30VR043:
SST31LF041A
SST30VR043
|
PDF
|
Equivalent of sw2 354
Abstract: sw2 354 8080 microprocessor Architecture Diagram cmos power TCP 8108 oasis F-173
Text: 8 Megabit Flash + 2 Megabit SRAM ComboMemory SST32LH802 Advance Information FEATURES: • Organized as 512K x16 Flash + 128K x16 SRAM or 512K x8 x2 Flash + 128K x8 x2 SRAM • Single 3.0-3.6V Read and Write Operations • Concurrent Operation – Read from or write to SRAM while
|
Original
|
SST32LH802
Sec498404
Equivalent of sw2 354
sw2 354
8080 microprocessor Architecture Diagram
cmos power TCP 8108
oasis
F-173
|
PDF
|
SST30VR041
Abstract: 4011 PIN DIAGRAM
Text: 4 Megabit ROM + 1 Megabit SRAM ROM/RAM Combo SST30VR041 Advance Information FEATURES: • Organized as 512K x8 ROM + 128K x8 SRAM • ROM/RAM combo on a monolithic chip • Equavalent ComboMemory Flash + SRAM : SST31LF041A for code development and pre-production
|
Original
|
SST30VR041
SST31LF041A
32-Pin
SST30VR041
MO-142
4011 PIN DIAGRAM
|
PDF
|
Untitled
Abstract: No abstract text available
Text: TMS29F040 524288 BY 8-BIT FLASH MEMORY SMJS820B - APRIL 1996- REVISED NOVEMBER 1987 • • • • • • • • • • Single Power Supply 5 V± 10% - 3.3 V ± 0.3 V - See ’29LF040/’29VF040 Data Sheet Literature Number SMJS825 - 2.7 V to 3.6 V - See ’29LF040/’29VF040
|
OCR Scan
|
SMJS820B
TMS29F040
29LF040/
29VF040
SMJS825)
A18A17
|
PDF
|
GA1030
Abstract: No abstract text available
Text: TMS29F040 524288 BY 8-BIT FLASH MEMORY . • • • • • • • • • • SMJS820B - APRIL 1996 - REVISED NOVEMBER 1997 Single Power Supply 5 V ± 10% - 3.3 V ± 0.3 V - See ’29LF040/ 29VF040 Data Sheet Literature Number SMJS825 - 2.7 V to 3.6 V - See ’29LFO40/'29VFO4O
|
OCR Scan
|
SMJS820B
TMS29F040
29LF040/
29VF040
SMJS825)
29LFO40/
29VFO4O
GA1030
|
PDF
|
|
|
ZUA12
Abstract: ZUA13
Text: HM62W8511H Series 524288-word x 8-bit High Speed CMOS Static RAM HITACHI ADE-203-750 Z Preliminary Rev. 0.0 Feb. 27, 1997 Description The HM62W8511H is an asyncronous high speed static RAM organized as 5 12-kwordx 8-bit. It has realized high speed access time (10/12/15 ns) with employing 0.35 |im CMOS process and high speed circuit
|
OCR Scan
|
HM62W8511H
524288-word
ADE-203-750
12-kwordx
400-mil
36-pin
ns/15
D-85622
ZUA12
ZUA13
|
PDF
|
74LS384
Abstract: SRG8 LS384
Text: TYPES SN54LS384, SN74LS384 8-BIT BY 1-BIT TWO’S-COMPLEMENT MULTIPLIERS D 24 19 , J A N U A R Y 1981 - Tw o's-C om plem ent M u ltip lication R E V IS E D D E C E M B E R 1 9 8 3 S N 5 4 L S 3 8 4 . . . J PACKAGE S N 7 4 L S 3 8 4 . . . J OR N PACKAGE Magnitude O n ly M u ltip lication
|
OCR Scan
|
SN54LS384,
SN74LS384
74LS322
74LS384
SRG8
LS384
|
PDF
|
Untitled
Abstract: No abstract text available
Text: MITSUBISHI M E M O R Y C A R D S T A T I C R A M CAR DS MF31M1-M6DAPXX MF32M1-M6DAPXX 16-bit Data Bus Static R A M Card Connector Ty pe Two-piece 60-pin / ' —-. . E l e c t ro s t at i c d i s c h a r g e p r o te ct io n to 25kV DESCRIPTION Mitsubishi's
|
OCR Scan
|
16-bit
MF31M1-M6DAPXX
MF32M1-M6DAPXX
60-pin
60-pin
MF31M
MF32M
|
PDF
|
harris 5330
Abstract: No abstract text available
Text: HARRIS SEfTICOND SECTOR 33 HARRIS T ' ID E D 1 4302271 0013aS5 M I HA-5330/883 3 r very High Speed Precision Monolithic Sample and Hold Amplifier January 1989 Features Description • This Circuit Is Processed in Accordance to Mll-Std883 and Is Fully Conformant Under the Provisions of
|
OCR Scan
|
0013aS5
HA-5330/883
Mll-Std883
500ns
10VStep
900ns
11VtoÂ
HA-5330/883
20Vp-p,
100kHz
harris 5330
|
PDF
|
29VF040
Abstract: TMS29F040 29VF04 SMJS820B
Text: TMS29F040 524288 BY 8-BIT FLASH MEMORY SM JS820B - AP R IL 1996 - REVISED N O VEM BER 1997 • • • • Single Power Supply 5 V ± 10% - 3.3 V ± 0.3 V - See ’29LF040/’29VF040 Data Sheet Literature Number SMJS825 - 2.7 V to 3.6 V - See ’29LF040/’29VF040
|
OCR Scan
|
29LF040/
29VF040
SMJS825)
Ty1996-REVISED
R-PDSO-G32)
4040097/E
29VF040
TMS29F040
29VF04
SMJS820B
|
PDF
|