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    AGERE RSP Search Results

    AGERE RSP Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    tag 8833

    Abstract: RSP RELAY scr tag 89 marking RSP tag b1
    Text: Product Brief June 2001 PayloadPlus Agere System Interface Introduction Agere System Interface The Agere Systems PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full


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    PDF PB01-131NP tag 8833 RSP RELAY scr tag 89 marking RSP tag b1

    tag 8833

    Abstract: RSP RELAY scr tag 89 marking RSP asi bus MASTER BUS asi
    Text: Preliminary Product Brief April 2000 NPASI PayloadPlus Agere System Interface Introduction Agere System Interface The Lucent PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full programmability.


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    PDF 2000Lucent tag 8833 RSP RELAY scr tag 89 marking RSP asi bus MASTER BUS asi

    Agere ASI

    Abstract: Agere FPP
    Text: Product Brief April 2001 PayloadPlus Fast Pattern Processor Introduction Fast Pattern Processor The Agere Systems PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full


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    PDF PB01-132NP Agere ASI Agere FPP

    scheduling

    Abstract: Agere ASI POS-PHY utopia
    Text: Product Brief April 2001 PayloadPlus Routing Switch Processor Introduction The Routing Switch Processor The Agere Systems PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full


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    PDF progra316, PB01-133NP scheduling Agere ASI POS-PHY utopia

    Agere ASI

    Abstract: a bus system with two 7495 "routing tables"
    Text: Product Brief November 2001 PayloadPlus Fast Pattern Processor Introduction Fast Pattern Processor The Agere Systems PayloadPlus architecture provides a unique hardware and software combination that delivers high-speed processing for multiple communication protocols with full


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    PDF PB01-132NP Agere ASI a bus system with two 7495 "routing tables"

    Agere ASI

    Abstract: APP550 NP10 TM10 "L2TP"
    Text: Product Brief Brief Product September 2002 September 2002 Advanced PayloadPlus Network Processor APP550 Introduction The Agere Systems Advanced PayloadPlus Network Processor device is the latest addition to the PayloadPlus family of products. It offers a


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    PDF APP550) PB02-024NP-2 PB02-024NP-1) Agere ASI APP550 NP10 TM10 "L2TP"

    Transistor KU 607 VC

    Abstract: OC-40 a bus system with two 7495
    Text: Product Brief April 2001 PayloadPlus Voice Packet Processor Introduction • The Voice Packet Processor VPP is part of the Agere Systems PayloadPlus family of network processors. The VPP is designed to fit on the data path between the Fast Pattern Processor (FPP)


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    PDF OC-12, PB02-015NP Transistor KU 607 VC OC-40 a bus system with two 7495

    Agere RSP

    Abstract: Agere ASI OC-40
    Text: Product Brief April 2001 Voice Packet Processor Introduction • The Voice Packet Processor VPP is part of the Agere Systems PayloadPlus family of network processors. The VPP is designed to fit on the data path between the Fast Pattern Processor (FPP)


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    PDF OC-12, Agere RSP Agere ASI OC-40

    47AB

    Abstract: SCD1U16V3KX BCB25 BC536 BC163 216t9 sis645dx foxconn WISTRON BC466
    Text: CLK GEN TOUCAN2 DesKtop-CPU Northwood 2.2~3.06GHz ICS:ICS952004AG DDRBUF:ICS93732 3,4 5,6 VRAM*2 FSB 533/400MHz K4D263238M-QC40 CRT 17 2.5V 200MHz/266MHz DDR * 2 11,12,13 SiS962 24 CD-ROM AGP 4X W/RTC 15" MII LAN MAC PHY 20,21,22,23 1394 conn. Agere FW802A


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    PDF ICS952004AG ICS93732 06GHz K4D263238M-QC40 533/400MHz 200MHz/266MHz 47Y01 SiS645DX 66MHz 16bits/533MBs 47AB SCD1U16V3KX BCB25 BC536 BC163 216t9 foxconn WISTRON BC466

    agere VPP

    Abstract: data sheet ic 7495 gvrp 7495 ic data sheet MPC750 tornado "Spanning Tree" "OSPF" 8021G
    Text: Product Brief June 2001 Tornado Managed Systems and PayloadPlus Introduction The growth of the Internet brings constant challenges to vendors who supply data networking infrastructure equipment, and to manufacturers, who are expected to provide increasingly higher performance, lower cost


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    PDF PB01-141NP agere VPP data sheet ic 7495 gvrp 7495 ic data sheet MPC750 tornado "Spanning Tree" "OSPF" 8021G

    LG1627BXC

    Abstract: TADM042G5 TDAT042G5 TRCV012G5 TTRN012G5 IXF1002 IXF440 transmit data through ethernet to fpga by vhdl
    Text: Product Brief June 2001 Gigabit Ethernet/Fast Ethernet POS-PHY Bridge Overview The gigabit Ethernet GbE /fast Ethernet POS-PHY bridge enables system solutions to be created for two different applications. The first application involves transporting GbE frames or 10 Mbits/s/100 Mbits/s


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    PDF Mbits/s/100 PB01-098NCIP PB01-029NCIP) LG1627BXC TADM042G5 TDAT042G5 TRCV012G5 TTRN012G5 IXF1002 IXF440 transmit data through ethernet to fpga by vhdl

    RBS 2202

    Abstract: SA4-13 SA5-27 LC1 D09 01 SR10 SR12 T7633 PR70 TFRA08C133BAL3-db LC1 D25 004
    Text: Data Sheet February 2003 TFRA08C133BAL3 OCTAL T1/E1 Framer Features • Eight independent T1/E1 transmit and receive framers. ■ Internal DS1 transmit clock synthesis—no external oscillator necessary. ■ Comprehensive alarm reporting and performance monitoring:


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    PDF TFRA08C133BAL3 DS03-055AGG DS02-240BBAC) RBS 2202 SA4-13 SA5-27 LC1 D09 01 SR10 SR12 T7633 PR70 TFRA08C133BAL3-db LC1 D25 004

    M25C22

    Abstract: SA4-13 SA5-27 T7115a Y18-Y19 RHS25
    Text: Data Sheet February 2003 TFRA08C133BAL3 OCTAL T1/E1 Framer Features • Eight independent T1/E1 transmit and receive framers. ■ Internal DS1 transmit clock synthesis—no external oscillator necessary. ■ Comprehensive alarm reporting and performance monitoring:


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    PDF TFRA08C133BAL3 DS03-055MPIC DS02-240BBAC) M25C22 SA4-13 SA5-27 T7115a Y18-Y19 RHS25

    RBS 2202

    Abstract: SA4-13 SA5-27 LC1 D09 10 PR70 SR10 SR12 T7633 TFRA08C13 AMI encoding circuit diagram
    Text: Preliminary Data Sheet May 2002 TFRA08C13 OCTAL T1/E1 Framer Features • Eight independent T1/E1 transmit and receive framers. ■ Internal DS1 transmit clock synthesis—no external oscillator necessary. ■ Comprehensive alarm reporting and performance


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    PDF TFRA08C13 DS02-240BBAC DS00-190PDH) RBS 2202 SA4-13 SA5-27 LC1 D09 10 PR70 SR10 SR12 T7633 AMI encoding circuit diagram

    Untitled

    Abstract: No abstract text available
    Text: Preliminary Product Brief April 2000 SDE PayloadPlus Software Development Environment The Lucent family of PayloadPlus network processors is designed to support a high degree of programmability at wire speeds. This approach allows hardware designers to build equipment


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    PDF 2000Lucent

    AD10

    Abstract: AD11 AD12 AD14 AD17 FW322
    Text: Data Sheet, Rev. 3 December 2001 FW322 1394A PCI PHY/Link Open Host Controller Interface Features • 1394a-2000 OHCI link and PHY core function in single device: — Enables smaller, simpler, more efficient motherboard and add-in card designs by replacing two


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    PDF FW322 1394a-2000 1394a-2000, core-lin12-4106) DS01-046CMPR-3 DS01-046CMPR-2) AD10 AD11 AD12 AD14 AD17 FW322

    RBS 2202

    Abstract: 2202 bts diode S4 68a T7630 SA5-27 TND 027 YM SA4-13 f 4556 PR70 Lucent SLC 2000
    Text: Preliminary Data Sheet May 2002 T7630 Dual T1/E1 5.0 V Short-Haul Terminator Terminator-II Features • The T7630 Dual T1/E1 Terminator consists of two independent, highly integrated, software-configurable, full-featured short-haul transceiver/framers. The T7630 provides glueless interconnection from a


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    PDF T7630 DS02-243BBAC DS00-191TIC) RBS 2202 2202 bts diode S4 68a SA5-27 TND 027 YM SA4-13 f 4556 PR70 Lucent SLC 2000

    eeprom H840

    Abstract: 1394 schematic 1394 SCHEMATIC DIAGRAM H808 h840 pm h800 current switch AD10 AD11 AD12 AD14
    Text: Data Sheet, Rev. 1 May 2001 FW323 05 1394A PCI PHY/Link Open Host Controller Interface Features • 1394a-2000 OHCI link and PHY core function in single device: — Enables smaller, simpler, more efficient motherboard and add-in card designs by replacing two


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    PDF FW323 DS01-124CMPR-1 eeprom H840 1394 schematic 1394 SCHEMATIC DIAGRAM H808 h840 pm h800 current switch AD10 AD11 AD12 AD14

    Untitled

    Abstract: No abstract text available
    Text: Data Sheet May 2004 FW322 06 T100 1394A PCI PHY/Link Open Host Controller Interface Features „ 1394a-2000 OHCI link and PHY core function in a single device: — 100-pin TQFP package also available in a leadfree package; see ordering information on page 85.


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    PDF FW322 1394a-2000 100-pin DS04-179CMPR

    FW3227

    Abstract: No abstract text available
    Text: Data Sheet November 2004 FW322 06 T100 1394A PCI PHY/Link Open Host Controller Features „ „ „ supporting 400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic — Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders — While unpowered and connected to the bus, will


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    PDF FW322 1394a-2000 100-pin DS05-030CMPR DS04-179CMPR) FW3227

    0C00

    Abstract: FW322 PCI32 S100 S200 S400 T100
    Text: Data Sheet, Rev. 2 October 2006 FW322 06 T100 1394a PCI PHY/Link Open Host Controller Features „ 1394a-2000 OHCI link and PHY core function in a single device: — 100-pin TQFP package also available in a lead-free package; see ordering information on page 85


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    PDF FW322 1394a 1394a-2000 100-pin applica8109-9138 DS05-030CMPR-2 DS05-030CMPR-1) 0C00 PCI32 S100 S200 S400 T100

    eeprom H840

    Abstract: H808 h840 0C00 FW322 PCI32 S100 S200 S400 T100
    Text: Data Sheet, Rev. 1 December 2005 FW322 06 T100 1394a PCI PHY/Link Open Host Controller Features „ 1394a-2000 OHCI link and PHY core function in a single device: — 100-pin TQFP package also available in a lead-free package; see ordering information on page 85.


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    PDF FW322 1394a 1394a-2000 100-pin applicatio18109-9138 DS05-030CMPR-1 DS05-030CMPR) eeprom H840 H808 h840 0C00 PCI32 S100 S200 S400 T100

    FW322

    Abstract: FW323 PCI32 S100 S200 S400 T100 L-FW321-06-NV129-DB
    Text: Data Sheet November 2005 FW321 NV129 1394a PCI PHY/Link Open Host Controller Interface 1 Features • 129-ball VTFSBGA lead-free package. ■ 1394a-2000 OHCI link and PHY core function in a single device: — Single-chip link and PHY enable smaller, simpler, more efficient motherboard and add-in card


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    PDF FW321 NV129 1394a 1394a-2000 1394a-2000, DS06-025CMPR FW322 FW323 PCI32 S100 S200 S400 T100 L-FW321-06-NV129-DB

    OR3LP26B

    Abstract: OR3T20 ORT8850 7ba2 diode pb7d
    Text: Preliminary Data Sheet April 2001 PayloadPlus /APC UTOPIA Slave Bridge Introduction Features The PayloadPlus/ATM port controller APC universal test and operations PHY interface for ATM (UTOPIA) slave bridge, also known as the PayloadPlus APC wedge (PAW) or the Atlanta™ interface


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    PDF OR3T20 DS01-212NCIP OR3LP26B ORT8850 7ba2 diode pb7d