vero pk 100 monovolt
Abstract: vero pk 100 116-010219G 116-410018B vero pk 120 PK60 PK60-R PK75 116-410018B PK120 tri PK60
Text: 30 bis 240 Watt primärgetaktete AC/DC-Einschubnetzteile mit einer Ausgangsspannung in 3HE und 6HE-Eurokassetten für den Einsatz in 19"-Baugruppenträgern nach DIN41494 PK-Serie: MONOVOLT AC/DC-Netzteile • Kompakter Aufbau in stabiler Alu-Kassette • Hohe Regelgenauigkeit
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Original
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DIN41494
PK60-R
EN60950,
PK120:
1350g
H15-Stecker
2-15V
-12-15V
PK120
vero pk 100 monovolt
vero pk 100
116-010219G
116-410018B
vero pk 120
PK60
PK75 116-410018B
PK120
tri PK60
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PDF
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vero pk 100 monovolt
Abstract: PK120 vero pk 100 pk60-r DIN41494 vero pk 120 vero pk 30 bivolt 116-010072C vero PK120 PK75 116-410018B
Text: 30 bis 240 Watt primärgetaktete AC/DC-Einschubnetzteile mit einer Ausgangsspannung in 3HE und 6HE-Eurokassetten für den Einsatz in 19"-Baugruppenträgern nach DIN41494 PK-Serie: MONOVOLT AC/DC-Netzteile • Kompakter Aufbau in stabiler Alu-Kassette • Hohe Regelgenauigkeit
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Original
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DIN41494
PK60-R
EN60950,
PK120:
1350g
H15-Stecker
2-15V
-12-15V
PK120
vero pk 100 monovolt
PK120
vero pk 100
DIN41494
vero pk 120
vero pk 30 bivolt
116-010072C
vero PK120
PK75 116-410018B
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PDF
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Untitled
Abstract: No abstract text available
Text: SHARC Embedded Processor ADSP-21261/ADSP-21262/ADSP-21266 SUMMARY Single-instruction multiple-data SIMD computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/ 40-bit extended precision floating-point computational units, each with a multiplier, ALU, shifter, and register file
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Original
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ADSP-21261/ADSP-21262/ADSP-21266
32-bit
floating-point/32-bit
40-bit
BC-136
ST-144
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PDF
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BM 1084
Abstract: ADSP-TS201Sw ADSP-TS201SWBP-050 ADSP-TS201SABP-050 ADSP-TS201SABP-060 ADSP-TS201S
Text: TigerSHARC Embedded Processor ADSP-TS201S a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a
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Original
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576-ball)
14-channel
32-bit
40-bit
64-bit
d576-Ball
576-Ball
ADSP-TS201SABP-060
ADSP-TS201SABP-050
BM 1084
ADSP-TS201Sw
ADSP-TS201SWBP-050
ADSP-TS201S
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PDF
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ADSP-TS201SWBP-050
Abstract: 7485 pin configuration ADSP-TS201S SYSCON 3 ADSP-TS201SABP-050 ADSP-TS201SABP-060 ADSP-TS201SwBP
Text: TigerSHARC Embedded Processor ADSP-TS201S a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a
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Original
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ADSP-TS201S
576-ball)
14-channel
BP-576
D04324-0-11/04
BP-576)
ADSP-TS201SWBP-050
7485 pin configuration
ADSP-TS201S
SYSCON 3
ADSP-TS201SABP-050
ADSP-TS201SABP-060
ADSP-TS201SwBP
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PDF
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B1151 Y
Abstract: b1333 DSP56000 DSP96002 B1571-1 b1151 3n14 B1432 D3S 59 B1402
Text: APPENDIX B DSP BENCHMARKS B.1 DSP96002 STANDARD DSP BENCHMARKS Program size and instruction cycle counts for the DSP56000/1 are in parentheses on the line following the DSP96002 program size and instruction cycle count. All floating-point data ALU operations are performed using single precision operations ".s" extension on
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Original
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DSP96002
DSP56000/1
B-204
B1151 Y
b1333
DSP56000
B1571-1
b1151
3n14
B1432
D3S 59
B1402
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PDF
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ts201
Abstract: ADSP-TS201S ADSP-TS201SYBP-050 PF 08112 BM 1084 ADSP-TS201 SDRAM ADSP-TS201SABP-050 ADSP-TS201SABP-060 ADSP-TS201SABPZ050 ADSP-TS201SABPZ060
Text: TigerSHARC Embedded Processor ADSP-TS201S • a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a
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Original
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ADSP-TS201S
576-ball)
14-channel
32-bit
BP-576
ts201
ADSP-TS201S
ADSP-TS201SYBP-050
PF 08112
BM 1084
ADSP-TS201 SDRAM
ADSP-TS201SABP-050
ADSP-TS201SABP-060
ADSP-TS201SABPZ050
ADSP-TS201SABPZ060
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PDF
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Untitled
Abstract: No abstract text available
Text: TigerSHARC Embedded Processor ADSP-TS201S • a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a
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Original
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ADSP-TS201S
576-ball)
14-channel
32-bit
BP-576
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PDF
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SMD phase shifter 0201
Abstract: ts201S ADSP-TS201SABP-050 ADSP-TS201SABP-060 l3bc
Text: TigerSHARC Embedded Processor ADSP-TS201S • a KEY FEATURES KEY BENEFITS Up to 600 MHz, 1.67 ns instruction cycle rate 24M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a
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Original
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576-ball)
14-channel
32-bit
40-bit
64-bit
BP-576
576-Ball
SMD phase shifter 0201
ts201S
ADSP-TS201SABP-050
ADSP-TS201SABP-060
l3bc
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PDF
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250M
Abstract: ADSP-TS101S BR70 TigerSHARC DSP Instruction set specification
Text: T a DSP Microcomputer ADSP-TS101S KEY FEATURES 250 MHz, 4.0 ns Instruction Cycle Rate 6M Bits of Internal—On-Chip—SRAM Memory 19 ؋ 19 mm 484-Ball or 27 ؋ 27 mm (625-Ball) PBGA Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, and a Register File
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Original
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ADSP-TS101S
484-Ball)
625-Ball)
ADSP-TS101SAB1-000
ADSP-TS101SAB2-000
B-625
B-484
250M
ADSP-TS101S
BR70
TigerSHARC DSP Instruction set specification
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PDF
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ADSP-TS203S
Abstract: ADSP-TS201
Text: TigerSHARC Embedded Processor ADSP-TS203S a KEY FEATURES KEY BENEFITS 500 MHz, 2.0 ns instruction cycle rate 4M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a multiplier, a shifter, and a register file
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Original
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ADSP-TS203S
576-ball)
10-channel
ADSP-TS203SABP-050
BP-576
C04326-0-11/04
ADSP-TS203S
ADSP-TS201
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PDF
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str F 6256
Abstract: tigersharc smd transistor 8g h9 AU 6256 ADSP-TS101SAB1Z000 EMU10 g23 SMD Transistor smd transistor AE3 W25 smd 250M
Text: TigerSHARC Embedded Processor ADSP-TS101S FEATURES BENEFITS 300 MHz, 3.3 ns instruction cycle rate 6M bits of internal—on-chip—SRAM memory 19 mm x 19 mm 484-ball or 27 mm × 27 mm (625-ball) PBGA package Dual computation blocks—each containing an ALU, a multiplier, a shifter, and a register file
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Original
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ADSP-TS101S
484-ball)
625-ball)
14-channel
perf85
B-625
B-484
B-6256
str F 6256
tigersharc
smd transistor 8g h9
AU 6256
ADSP-TS101SAB1Z000
EMU10
g23 SMD Transistor
smd transistor AE3
W25 smd
250M
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PDF
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Untitled
Abstract: No abstract text available
Text: TigerSHARC Embedded Processor ADSP-TS101S FEATURES BENEFITS 300 MHz, 3.3 ns instruction cycle rate 6M bits of internal—on-chip—SRAM memory 19 mm x 19 mm 484-ball or 27 mm × 27 mm (625-ball) PBGA package Dual computation blocks—each containing an ALU, a multiplier, a shifter, and a register file
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Original
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ADSP-TS101S
484-ball)
625-ball)
14-channel
B-625
B-484
B-6256
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PDF
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ADSP-TS202S
Abstract: ADSP-TS202
Text: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES KEY BENEFITS 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a multiplier, a shifter, and a register file
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Original
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ADSP-TS202S
576-ball)
14-channel
ADSP-TS202SABP-050
BP-576
C04325-0-11/04
ADSP-TS202S
ADSP-TS202
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PDF
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smd w20
Abstract: adsp ts201 link port ts201 SMD transistor k23 y6 smd transistor 32X32 ADSP-TS202S
Text: TigerSHARC Embedded Processor ADSP-TS202S Preliminary Technical Data KEY FEATURES KEY BENEFITS 500 MHz, 2.0 ns Instruction Cycle Rate 12M Bits of Internal—On-Chip—DRAM Memory 25x25 mm 576-Ball Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, and a Register File
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Original
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ADSP-TS202S
576-Ball)
High-PerforADSP-TS202SABP-X
12Mbit
BP-576
C00000-0-03/03
smd w20
adsp ts201
link port ts201
SMD transistor k23
y6 smd transistor
32X32
ADSP-TS202S
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PDF
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EMU10
Abstract: W25 smd 250M ADSP-TS101S epd driver ic epd source driver ic fir compiler v5 B625 0x0380000
Text: T a Embedded Processor ADSP-TS101S KEY FEATURES 300 MHz, 3.3 ns Instruction Cycle Rate 6M Bits of Internal—On-Chip—SRAM Memory 19 mm ؋ 19 mm 484-Ball or 27 mm ؋ 27 mm (625-Ball) PBGA Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, and a Register File
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Original
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ADSP-TS101S
484-Ball)
625-Ball)
C03164
EMU10
W25 smd
250M
ADSP-TS101S
epd driver ic
epd source driver ic
fir compiler v5
B625
0x0380000
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PDF
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epd source driver ic
Abstract: EMU10 250M ADSP-TS101S epd driver ic U20-U21
Text: TigerSHARC Embedded Processor ADSP-TS101S a KEY FEATURES KEY BENEFITS 300 MHz, 3.3 ns instruction cycle rate 6M bits of internal—on-chip—SRAM memory 19 mm x 19 mm 484-ball or 27 mm × 27 mm (625-ball) PBGA package Dual computation blocks—each containing an ALU, a multiplier, a shifter, and a register file
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Original
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ADSP-TS101S
484-ball)
625-ball)
14-channel
B-625,
B-484,
B-625
B-484
D03164-0-12/04
epd source driver ic
EMU10
250M
ADSP-TS101S
epd driver ic
U20-U21
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PDF
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3564 K
Abstract: SD-35978-001
Text: DO NOT SCALE DRAWING DIMENSION IN METRIC PROJECT NO. 1 SIMILAR ITEM DWG. NO. SD-35978-001 ^ g-oo e ^- 3.2 f r t-11- REVISED ECN NO. KOR2002-0017 DRWN: K.S.KIM 010917> CHK: J.K.OH APPR: C.W.LEE_ DESCRIPTION L j 1- n -j 8 7.7*03 H- HO O > to o aLU
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OCR Scan
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P0LYAMIDE66
UL94V-0
PS-35978-001
35978041LS
WK990507)
SD35978AB
SD-35978-001
3564 K
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PDF
|
Untitled
Abstract: No abstract text available
Text: Customer Information Sheet DRAWING No.'. M90-3101F10SL-3S SHEET 2 OF 2 IF IN D O U B T -A S K THIRD ANGLE PROJECTION I ALL DIMENSIONS IN mm NOT TO SCALE SPECIFICATIO NS: MATERIAL: 5 / 8 - 2 4 U N E F -2 Ä SHELL = ALU M IN IUM ALLO Y INSULATO R = PO LYCHLOROPRENE
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OCR Scan
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M90-3101F10SL-3S
500Hz
IL-STD-1344,
IL-STD-1344
M90-3101F14S-6S
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PDF
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Untitled
Abstract: No abstract text available
Text: A DRAWING MADE IN AMERICAN PROJECTION | 1954. BY AM P INCORPORATED, ALU RIGHTS R E SE R V E D . AM P PRODUCTS COVERED BY PA TEN TS AND/OR PA TEN TS PEN D IN G . REVISIONS I ! 1 APPROVED ' '~ A 'REDRAWN, RcVi'ADC-cD 2 - 2 NR5£^'0ft4 eB/l Æ *7;V Si ¿-25-¿7
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OCR Scan
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\comb\2-32510-1
29-May-2000
SPADE-024
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PDF
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268-5400
Abstract: weitek 268-5400-00 WTL1032 1u040 WTL1033 J1439
Text: A- B, W OODARD & AS SO C INNOVATIONS IN MICROSYSTEM TECHNOLOGY WTL1032 WTL1033 4 0 8 7 3 3 -7 3 5 3 High-Speed 32-Bit IEEE Floating Point Multiplier High-Speed 32-Bit IEEE Floating Point ALU Features A complete floating-point arithmetic solution for high-speed processors
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OCR Scan
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WTL1032
32-Bit
WTL1033
16-bit
100ns
200ns
900ns
1032JC/1033JC
268-5400
weitek
268-5400-00
1u040
J1439
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PDF
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Untitled
Abstract: No abstract text available
Text: ft i~ 'TH!RD ANGLE PROJECTION c 1980* e*x—- xi - C i s f t s v AMP Japa*; Ue. ALU R<CHT5 RESERVES. AMP (>«0£XJCTS COVEftEO BY PATENTS ANO OR PATEMTS PSKOf« AMP 2.54 xnsB 2. 54 x.n=B e E3 3 m r J _4a 34=. 3S. U tiL f c iS & ( M J ( S -6 OJajui ? m -4
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OCR Scan
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PDF
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z414
Abstract: socket SELF TAPPING SCREW TERMI POINT Z404 screw 4-40
Text: DRAWING MADE IN AM ERICAN PROJECTION S 1 9 7 2 BY A M P INCORPORATED. ALU RIGHTS RESERVED . AM P PRODUCTS COVERED BY P A T E N T S AND/OR P A T E N T S PENDIN G . 500 WARNING DO NOT O C t£ TOOL WITHOUT CLIPS / MANDREL INSTALLED. .6 3 7.62. N O TE: I. FOR REPLACEMENT OF PART5 OTHER THAN LISTED, TOOL
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OCR Scan
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Z4133&
306S35
Z404/9-3
z414
socket SELF TAPPING SCREW
TERMI POINT
Z404
screw 4-40
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PDF
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Untitled
Abstract: No abstract text available
Text: A. e PREHj INNOVATIONS IN MICROSYSTEM TECHNOLOGY WOODARD & ASSOC. ä\ T / ä 408 7 3 3 -7 3 5 3 WTL1032 High-Speed 32-Bit IEEE Floating Point Multiplier WTL1033 High-Speed 32-Bit IEEE Floating Point ALU Features A co m p lete flo atin g -p o in t a rith m etic solu tion
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OCR Scan
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WTL1032
32-Bit
WTL1033
1032JC/1033JC
1032JM/1033JM
1032LC/1033LC
1032LM/1033LM
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PDF
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