Untitled
Abstract: No abstract text available
Text: 54AC11109, 74AC11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET TI0066— D2957, M ARCH 1987— REVISED M ARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11109 . . . J PACKAGE 74AC11109 . . . D OR N PACKAGE TOP VIEW
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OCR Scan
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54AC11109,
74AC11109
TI0066--
D2957,
500-mA
STD-883C
300-mil
54AC11109
74AC11109
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PDF
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Untitled
Abstract: No abstract text available
Text: TIBPAL22V10-20M HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPSQ12A - D3523, JUNE 1 9 9 0 -R E V IS E D MARCH 1992 JT P A C K A G E Second-Generation PLD Architecture TO P V IE W High-Performance Operation: fmax (External Feedback). . . 33.3 MHz
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OCR Scan
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TIBPAL22V10-20M
SRPSQ12A
D3523,
SRPS012A
10-BIT
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PDF
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Untitled
Abstract: No abstract text available
Text: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to
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OCR Scan
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54AC11032,
74AC11032
TI0060--
D2957,
500-mA
300-mil
54AC11032
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PDF
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tr8c
Abstract: TMS28F200
Text: TMS28F20ÛBZT, TMS28F200BZB 262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES SWS2dOO - JUNE 1 9 9 4 - REVISED SEPTEMBER 1997 • ■ I I I • • • • • • • • • • Organization . . . 262144 by 8 bits 131072 by 16 bits Array-Blocking Architecture
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OCR Scan
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TMS28F20
TMS28F200BZB
8-BIT/131072
16-BIT
96K-Byte
128K-Byte
16K-Byte
28F200B2x70
28F200BZX80
28F200BZX90
tr8c
TMS28F200
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PDF
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Untitled
Abstract: No abstract text available
Text: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations
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OCR Scan
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54AC11021
74AC11021
D2957.
500-mA
300-mll
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PDF
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Untitled
Abstract: No abstract text available
Text: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise
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OCR Scan
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54AC11002,
74AC11002
D2957,
500-mA
300-mil
54AC11002
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PDF
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i486
Abstract: No abstract text available
Text: SN74BCT2141 2-WAY 8K x 18 SYNCHRONOUS CACHE DATA RAM D3613. A UG UST 1990 2-Way 8K x 18 Bit Architecture FN PACKAGE TOP VIEW Synchronous Read and Write Access at 50 MHz Clock Frequency Incorporates Burst Counter for Burst-Read (Read-Hit) Cycles or Burst-Write (Line-Fill)
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OCR Scan
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SN74BCT2141
D3613.
I486TM
DQ13s
BCT2141
i4861
i486
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PDF
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NCC equivalent
Abstract: No abstract text available
Text: TMS29F400T, TMS29F400B 524288 BY 8-BIT/262144 BY 16-BIT FLASH M EMORIES • I • Single Power Supply Supports 5 V ± 10% Read/Write Operation I I • Organization . . . I • Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector - Two 8K-Byte/4K-Word Parameter Sectors
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OCR Scan
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TMS29F400T,
TMS29F400B
8-BIT/262144
16-BIT
SMJS843A
44-Pin
48-Pin
8-Blf/262144
NCC equivalent
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PDF
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Untitled
Abstract: No abstract text available
Text: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise
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OCR Scan
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54ACT11002
74ACT11002
SCAS003A
D2957,
500-mA
300-mll
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PDF
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D2957
Abstract: No abstract text available
Text: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations
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OCR Scan
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500-mA
300-mll
AC11240
AC11244,
D2957
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PDF
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74AC11520
Abstract: No abstract text available
Text: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations
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OCR Scan
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54AC11520
74AC11520
D2957,
500-mA
300-mil
54AC11520
74AC11S20.
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PDF
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2a117
Abstract: No abstract text available
Text: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to
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OCR Scan
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54AC11158,
74AC11158
TI010
500-mA
300-mil
54AC11158
74AC11158
2a117
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PDF
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D3348
Abstract: 74AC11151
Text: 74AC11151 1-0F-8 DATA SELECTOR/MULTIPLEXER D3348, JUNE 1989 - REVISED APRIL 1993 * 8-Llne to 1-Llne Multiplexers Can Perform as Boolean Function Generators, Parallel-to-Serlal Converters, or Data Source Selectors * Flow-Through Architecture Optimizes PCB Layout
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OCR Scan
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74AC11151
D3348,
500-mA
300-mil
D3348
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PDF
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Untitled
Abstract: No abstract text available
Text: 54AC 11004, 74AC11004 HEX INVERTERS TI0044— D2957, FEBRUARY 1068— REVISED M ARCH 1990 54AC11004 . . . J PACKAGE 74AC11004 . . . DW OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin Vq c and GND Configurations to
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OCR Scan
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74AC11004
TI0044--
D2957,
500-mA
300-mil
54AC11004
74AC11004
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PDF
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54AC11181
Abstract: TI018
Text: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T I0184— D 3119, APRIL 1989— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE TOP VIEW Minimize High-Speed Switching Noise
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OCR Scan
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54AC11181,
74AC11181
I0184--
500-mA
300-mil
54AC11181
74AC11181
54AC11181
TI018
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PDF
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Untitled
Abstract: No abstract text available
Text: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0053— D 2957, JUNE 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54ACT11020 . . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout
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OCR Scan
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54ACT11020,
74ACT11020
TI0053--
54ACT11020
74ACT11020
500-mA
300-mil
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PDF
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TI009
Abstract: No abstract text available
Text: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to
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OCR Scan
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54AC11643,
I0095--
D2957,
500-mA
300-mil
54AC11643
74AC11643
TI009
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PDF
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D2957
Abstract: 1987-REVISEDAPRIL
Text: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted
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OCR Scan
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54ACT11030
74ACT11030
D2957.
1987-REVISEDAPRIL
500-mA
300-mll
D2957,
D2957
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PDF
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74AC108
Abstract: so 54 t 74AC11066
Text: 54AC11086, 74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES TI0152— D3375, N O VEM BER 1989 • Flow-Through Architecture to Optimize PCB Layout 54AC11086 . . . J PACKAGE 74AC11086 . . . D OR N PACKAGE TOP VIEW • Center-Pin Vqc and GND Configurations to
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OCR Scan
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54AC11086,
74AC11086
TI0152--
D3375,
500-mA
300-mil
74AC108
so 54 t
74AC11066
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PDF
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Untitled
Abstract: No abstract text available
Text: y UNITRODE UC1524A UC2S24A UC3524A Advanced Regulating Pulse Width Modulators DESCRIPTION FEATURES Fully Interchangeable with Standard UC1524 Family The UC1524A family of regulating PWM ICs has been designed to retain the same highly versatile architecture of the industry standard UC1524 SG1524
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OCR Scan
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UC1524
UC1524A
UC2S24A
UC3524A
UC1524
SG1524)
UC1524A,
200ns
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PDF
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ti0041
Abstract: No abstract text available
Text: 54ACT11000, 74ACT11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES T I0041— D2957, JUNE 1967— REVISED M ARCH 1990 • Inputs are TTL-Voltage Compatible 5 4 A C T 11 0 00 . . . J P ACKA G E 7 4 A C T 1 1000 . . . D O R N PACKA GE • Flow-Through Architecture to Optimize PCB
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OCR Scan
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54ACT11000,
74ACT11000
I0041--
D2957,
500-mA
300-mil
ti0041
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PDF
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Untitled
Abstract: No abstract text available
Text: 54AC11074,74AC11074 DUAL D-TYPE POSUIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET D2957, D E C E M B E R 1986 - REVISED A P R IL 1983 54AC11074. . . J PACKAGE 74AC11074. . . D, N, OR PW PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout
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OCR Scan
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54AC11074
74AC11074
D2957,
500-mA
300-mil
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PDF
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Untitled
Abstract: No abstract text available
Text: 54AC11020,74AC11020 DUAL 4-INPUT POSITIVE-NAND GATES D2957, MAHCH 1987-REVISEDAPRIL1993 54AC11020. . . J PACKAGE 74AC11020. . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise
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OCR Scan
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54AC11020
74AC11020
D2957,
1987-REVISEDAPRIL1993
500-mA
300-mil
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PDF
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ACT8841
Abstract: sn74act8841 SN74AS8840 S/ACT8841
Text: SN 74A C T8841 Digital Crossbar Switch The S N 7 4 A C T 8 8 4 1 is a single-chip digital crossbar sw itch that cost-effectively eliminates bottlenecks to speed data through com plex bus architectures. The 'A C T 8 8 4 1 has 16 four-bit bidirectional ports w hich can be connected in
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OCR Scan
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T8841
32-bit
16-port
SN74ACT8841
ACT8841
sn74act8841
SN74AS8840
S/ACT8841
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PDF
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