Untitled
Abstract: No abstract text available
Text: ESMT M52S32162A Revision History : Revision 1.0 Oct. 31, 2006 - Original Revision 1.1 (Mar. 02, 2007) - Modify VOH and VOL - Delete BGA ball name of packing dimensions Revision 1.2 (Apr. 27, 2007) - Rename BGA pin name (BA1 to NC ; BA0 to BA) - Modify DC Characteristics
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M52S32162A
M52S32162A
16Bit
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M52S32162A
Abstract: No abstract text available
Text: ESMT M52S32162A Revision History : Revision 1.0 Oct. 31, 2006 - Original Revision 1.1 (Mar. 02, 2007) - Modify VOH and VOL - Delete BGA ball name of packing dimensions Revision 1.2 (Apr. 27, 2007) - Rename BGA pin name (BA1 to NC ; BA0 to BA) - Modify DC Characteristics
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M52S32162A
16Bit
M52S32162A
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M52D32162A
Abstract: No abstract text available
Text: ESMT M52D32162A Revision History : Revision 1.0 Aug.16, 2006 - Original Revision 1.1 (Aug. 31,2006) -Modify VDD; VDDQ; tSAC; ICC1; ICC2PS; ICC6 spec Revision 1.2 (Apr. 24,2007) - Delete BGA ball name of packing dimensions Revision 1.3 (Apr. 27,2007) - Rename BGA pin name (BA1 to NC ; BA0 to BA)
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M52D32162A
16Bit
M52D32162A
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EM639165
Abstract: EM639165TS EM639
Text: EtronTech EM639165 8Mega x 16bits SDRAM Preliminary Rev 1.0, 2/2001 Features Pin Assignment (Top View) • Single 3.3 ± 0.3V power supply • Fast clock rate - PC133: 133 MHz (CL3) - PC100: 100 MHz (CL2) • Fully synchronous operation referenced to clock
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EM639165
16bits
PC133:
PC100:
cycles/64ms
54-pin
EM639165
EM639165TS
EM639
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Untitled
Abstract: No abstract text available
Text: PRELIMINARY DATA SHEET 4GB Registered DDR3 SDRAM DIMM EBJ42RE8BAFA 512M words x 72 bits, 4 Ranks Specifications Features • Density: 4GB • Organization 512M words × 72 bits, 4 ranks • Mounting 36 pieces of 1G bits DDR3 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory
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EBJ42RE8BAFA
240-pin
1066Mbps/800Mbps
M01E0706
E1307E20
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EBJ42HE8BAFA
Abstract: inphi E1412E20 inphi 1320 E1412e
Text: DATA SHEET 4GB Registered DDR3 SDRAM DIMM EBJ42HE8BAFA 512M words x 72 bits, 4 Ranks Specifications Features • Density: 4GB • Organization 512M words × 72 bits, 4 ranks • Mounting 36 pieces of 1G bits DDR3 SDRAM sealed in FBGA • Package: 240-pin socket type dual in line memory
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EBJ42HE8BAFA
240-pin
1066Mbps/800Mbps
M01E0706
E1412E20
EBJ42HE8BAFA
inphi
E1412E20
inphi 1320
E1412e
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Untitled
Abstract: No abstract text available
Text: ESMT M12L32162A Revision History Revision 0.1 Aug. 11 2006 - Original Revision 0.2 (Mar. 20 2007) - Add BGA package Revision 0.3 (Apr. 27 2007) - Rename BGA pin name (BA1 to NC; BA0 to BA) - Modify DC Characteristics Revision 0.4 (Sep. 28 2007) - add speed –5 sepc.
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M12L32162A
M12L32162A
16Bit
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54PIN
Abstract: M12L32162A M12L32162A-7BG M12L32162A-7TG
Text: ESMT Preliminary M12L32162A Revision History Revision 0.1 Aug. 11 2006 - Original Revision 0.2 (Mar. 20 2007) - Add BGA package Revision 0.3 (Apr. 27 2007) - Rename BGA pin name (BA1 to NC; BA0 to BA) - Modify DC Characteristics Elite Semiconductor Memory Technology Inc.
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M12L32162A
16Bit
M12L32162A
54PIN
M12L32162A-7BG
M12L32162A-7TG
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1995 AND sdram AND
Abstract: No abstract text available
Text: DATA SHEET 128M bits Self Terminated Interface DDR SDRAM DC0122A 4M words x 32 bits Description Pin Configurations The DC0122A is a 128M bits self terminated interface DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at
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DC0122A
DC0122A
144-ball
450MHz/400MHz/350MHz
M01E0107
E0288E20
1995 AND sdram AND
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tck9
Abstract: No abstract text available
Text: DATA SHEET 128M bits Self Terminated Interface DDR SDRAM DC0122A 4M words x 32 bits Description Pin Configurations The DC0122A is a 128M bits self terminated interface DDR SDRAM organized as 1,048,576 words × 32 bits × 4 banks. Read and write operations are performed at
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DC0122A
DC0122A
144-ball
M01E0107
E0288E30
tck9
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EDS1232AASE
Abstract: No abstract text available
Text: DATA SHEET 128M bits SDRAM EDS1232AASE 4M words x 32 bits Specifications Pin Configurations • Density: 128M bits • Organization 1M words × 32 bits × 4 banks • Package: 90-ball FBGA Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 3.3V ± 0.3V
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EDS1232AASE
90-ball
166MHz/133MHz
cycles/64ms
M01E0107
E0350E31
EDS1232AASE
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"Led Level Meter Driver"
Abstract: SLB-26
Text: Audio iCs LED level meter driver, 12-point x 2 channel, VU scale, bar display BA6820F / BA6822S / BA6822F The BA6 8 2 0 F,BA 6 8 2 2 S and B A 6822F are tw o-channel, 12-point LED drivers for VU -scale bar-level meters. The ICs are available in 22-pin SO P B A 6820F and BA6822F and 22-pin shrink-DIP (BA6822S) packages, and use a
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12-point
BA6820F
BA6822S
BA6822F
6822F
22-pin
6820F
BA6822F)
"Led Level Meter Driver"
SLB-26
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BAS70 73p
Abstract: No abstract text available
Text: Philips Semiconductors Product specification Schottky barrier double d iod es FEATURES B A S 7 0 series PINNING SOT23 (see Fig.la) • Low forward current DESCRIPTIO N • High breakdown voltage PIN • Guard ring protected BAS70 BAS70-04 BAS70-05 BAS70-06
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BAS70-04
BAS70-05
BAS70-06
BAS70
BAS70
BAS70 73p
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIS M 5 M 4 S 1 6 S 2 1 C T P -7 ,- 8 , - 1 0 16777216-BIT 2-BANK x 2Q97152-WORD BY 4-BIT SYNCHRONOUS DYNAMIC RAM some DESCRIPTION The M5M4S16S21CTP is a 2-bank x 2097152-word by 4-bit PIN CONFIGURATION (TOP VIEW) Synchronous DRAM, with SSTL* 1 interface. All inputs and out
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16777216-BIT
2Q97152-WORD
M5M4S16S21CTP
2097152-word
M5M4S16S21CTP-8
150MHz
125MHz
M5M4316S21CTP-10
100MHz
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T flip flop IC
Abstract: 74LS648 T flip flop IC CMOS
Text: M IT S U B IS H I HIGH SPEED CMOS M 74H C 648P/FP/D W P ^ OCTAL 3-S TA TE IN V E R TIN G BUS T R A N S C E IV E R AND D -T Y P E F L IP -F L O P D ESC R IPT IO N The M74HC648 is a semiconductor integrated circuit con PIN C O NFIG URATIO N TO P V IEW sisting of eight bus transceivers with inverted outputs.
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648P/FP/D
M74HC648
70MHz
74LSTTL
14-PIN
150mil
16-PIN
20P2V
20-PIN
T flip flop IC
74LS648
T flip flop IC CMOS
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs ' MH1S72CXJ-10,-12,-15 75,497,472-BIT 1,048,576-WQRD BY 72-BIT Synchronous DYNAMIC RAM PRELIMINARY Some of contents are subject to change without notice. DESCRIPTION PIN CONFIGURATION The MH1S72CXJ is an 1M word by 72-bit Synchronous dynamic RAM module and consists of five industry standard
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MH1S72CXJ-10
472-BIT
576-WQRD
72-BIT
MH1S72CXJ
72-bit
576-WORD
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74AC11648
Abstract: No abstract text available
Text: 74AC/ACT 11648 Signetics Octal Transceiver/Register w/Direction Pin 3-State , INV Objective Specification ACL Products GENERAL INFORMATION FEATURES C O N D IT IO N S T . s 25°C ; G N D = 0V; • Octal bidirectional bus interface SYMBOL • 3-State buffers
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74AC/ACT
74AC11648
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs SDRAM Rev.1.2 0cr97 M5M4V64S30ATP-8A,-8, -10 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M4V64S30ATP is a 4-bank x 2097152-word x 8-bit
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0cr97
M5M4V64S30ATP-8A
2097152-WORD
M5M4V64S30ATP
125MHz,
Oct97
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Untitled
Abstract: No abstract text available
Text: Philips Semiconductors Product Specification Octal transceiver/register with dual enable; 3-state FEATURES • • • • • • Wide supply voltage range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1 A. Flow-through pin-out architecture Inputs accept voltages upto
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74LVC652
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Untitled
Abstract: No abstract text available
Text: Product S pecification Philips S em iconductors Octal transceiver/register with dual enable; 3-state FEA TU R ES • • • • • • W ide supply voltag e range of 1.2 V to 3.6 V In accordance with JEDEC standard no. 8-1 A. Flow -through pin-out architecture
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74LVC652
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs SDRAM Rev.0.2 Jan'97 M 5 M 4 V 6 4 S 3 0 A T P -8 , "1 0 , "1 2 Preliminary 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M4V64S30ATP is a 4-bank x 2097152-word x 8-bit
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2097152-WORD
M5M4V64S30ATP
125MHz,
125MHz
100MHz
83MHz
M5M4V64S30ATP-8,
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs SDRAM Rev.0.2 Jan'97 M5M4V64S40ATP-8, "1 0, "1 2 Preliminary 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit
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M5M4V64S40ATP-8,
1048576-WORD
16-BIT)
M5M4V64S40ATP
16-bit
125MHz,
125MHz
100MHz
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Untitled
Abstract: No abstract text available
Text: MITSUBISHI LSIs SDRAM Rev.0.2 Ja n '97 M5M4V64S20ATP-8, -10, -12 Preliminary 64M (4-BANK x 4194304-WQRD x 4-BIT) Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice. PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit
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M5M4V64S20ATP-8,
4194304-WQRD
M5M4V64S20ATP
4194304-word
125MHz,
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8L-10L
Abstract: No abstract text available
Text: MITSUBISHI LSIs ^-, ._ SDRAM Rev.1.3 Mar'98 M5M4V64S30ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM Some of contents are subject to change without notice. PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M4V64S30ATP is a 4-bank x 2097152-word x 8-bit
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M5M4V64S30ATP-8A
2097152-WORD
M5M4V64S30ATP
125MHz,
8L-10L
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