FEC Encoder
Abstract: turbo fec
Text: EFEC20 IP Core DS-1034-1.2 Data Sheet The Altera 20% Enhanced Forward Error Correction EFEC20 IP core includes a highperformance encoder and decoder for Optical Transport Network (OTN) FEC applications. Bose-Chaudhuri-Hocquenghem (BCH) streaming turbo product codes
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EFEC20
DS-1034-1
EFEC20)
FEC Encoder
turbo fec
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AT91SAM
Abstract: atmel BCH codes 257975,BOSE atmel 418
Text: Features • Multibit Error Correcting Code • Algorithm based on binary shortened Bose, Chaudhuri and Hocquenghem BCH codes Programmable Error Correcting Capability: 2, 4, 8, 12 and 24 bit of errors per sector Programmable Sector Size: 512 bytes or 1024 bytes.
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32-bit
11038AS
26-Jan-10
AT91SAM
atmel
BCH codes
257975,BOSE
atmel 418
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FEC Encoder
Abstract: No abstract text available
Text: EFEC7 IP Core DS-1033-1.2 Data Sheet The Altera 7% Enhanced Forward Error Correction EFEC7 IP core includes a highperformance encoder and decoder for Optical Transport Network (OTN) FEC applications. Bose-Chaudhuri-Hocquenghem (BCH) streaming turbo product codes
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DS-1033-1
FEC Encoder
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TC3024
Abstract: vhdl code hamming vhdl coding for hamming code hamming decoder vhdl code hamming vhdl block diagram code hamming qpsk modulation VHDL CODE vhdl code for block turbo codes TC3014 TC3000
Text: TurboConcept 1, av. du Technopôle 29280 PLOUZANE FRANCE phone : +33 2 29 00 19 88 fax : +33 2 29 00 18 03 www.turboconcept.com TC3000 Turbo Product Code decoders Introducing turbo product codes with BCH “t=2” codes Customisable bitrate : 7 to 25 Mbits/s
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TC3000
TC3000
TC3011
TC3014
TC3022
APEX20K
TC3024
vhdl code hamming
vhdl coding for hamming code
hamming decoder vhdl code
hamming vhdl
block diagram code hamming
qpsk modulation VHDL CODE
vhdl code for block turbo codes
TC3014
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AHA4702
Abstract: LDPC Codes DVB-S2 ldpc Comtech Aha LDPC LDPC decoder DVB-s2 ldpc encoder LDPC aha block interleave pb4702
Text: comtech aha corporation PRELIMINARY PRODUCT BRIEF AHA4702 DVB-S2 Compliant LDPC/BCH Forward Error Correction FEC Decoder Core INTRODUCTION FEATURES The AHA4702 FEC decoder core is fully compliant with section 5.3 of the Digital Video Broadcast S2 (DVB-S2) standard. It is capable of
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AHA4702
AHA4702
PB4702
LDPC Codes
DVB-S2
ldpc
Comtech Aha LDPC
LDPC decoder
DVB-s2 ldpc encoder
LDPC aha
block interleave
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dwa 108 a
Abstract: 27mhz remote control IC H261 HMP8112 HMP8364 MD31 dwa 108 Variable Length Decoder VLD
Text: HMP8364 S E M I C O N D U C T O R PRELIMINARY H.261 Video CODEC June 1997 Features Description • Complete and Fully Compliant H.261 Codec Including Framing and BCH Error Detect/Correct The Harris H.261 Video Codec is a single-chip, high performance integrated circuit that simultaneously encodes and
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HMP8364
1-800-4-HARRIS
dwa 108 a
27mhz remote control IC
H261
HMP8112
HMP8364
MD31
dwa 108
Variable Length Decoder VLD
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CX24116
Abstract: DVB-S2 demodulator NXP cx24116 DVB-S2 Tuner demodulator 8PSK NXP Semiconductors DVb-S2 demodulator CX24118 DVB-S2 DVB-S2 chipset BPSK demodulator
Text: NXP DVB-S2 demodulator and FEC decoder CX24116 Advanced DVB-S2 demodulation for increased satellite throughput The CX24116 is based on an open DVB-S2 standard and offers an alternate path for service providers to use advanced modulation 8PSK with LDPC/BCH FEC. This will realize increased
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CX24116
CX24116
brb243
DVB-S2 demodulator
NXP cx24116
DVB-S2 Tuner demodulator
8PSK
NXP Semiconductors DVb-S2 demodulator
CX24118
DVB-S2
DVB-S2 chipset
BPSK demodulator
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G.975
Abstract: BCH encoder decoder rs 1023 rs decoder OTU2 framer
Text: G.975 I.4 EFEC IP Core DS-1036 Data Sheet The Altera G.975 I.4 Enhanced Forward Error Correction G.975 I.4 EFEC IP core demonstrates the International Telecommunication Union-Telecommunication Standardization Sector (ITU-T) G.975 standardized Reed-Solomon (RS) and BoseChaudhuri-Hocquenghem (BCH) super FEC algorithms. G.975 I.4 EFEC implements
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DS-1036
G.975
BCH encoder decoder
rs 1023
rs decoder
OTU2 framer
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EECO micro dip
Abstract: 594-0020 351002GS 350002GS 450035G 230057gb 350035GS EECO bcd dip switch 350135gs stripswitch
Text: EECO/Trans ico Micro Dips and StripSwitch Printed Circuit Board Switches Micro Dips 594-0005 594-0010 594-0015 594-0020 594-0025 594-0030 230056GB 230057GB 350008GS 351008GS 350108GS 350002GS of Fig. No. Pos. A A B C B B 10 16 8 8 8 10 EACH Switch Code 1-99 100-499
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230056GB
230057GB
350008GS
351008GS
350108GS
350002GS
351002GS
350102GS
350012GS
351012GS
EECO micro dip
594-0020
351002GS
350002GS
450035G
230057gb
350035GS
EECO bcd dip switch
350135gs
stripswitch
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SLC nand hamming code 512 bytes
Abstract: hamming code 512 bytes hamming code flash hamming ecc eMMC hamming encoder decoder 7 bit hamming code BOSE emmc controller datasheet NAND Flash MLC emmC
Text: What Types of ECC Should Be Used on Flash Memory? Application Note by Scott Chen 1. Abstract NOR Flash normally does not need ECC Error-Correcting Code . On the other hand, NAND requires ECC to ensure data integrity. NAND Flash includes extra storage on each page to store ECC code as well as other
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vml25
Abstract: AN44161A HSOP034-P-0300B
Text: DATA SHEET Part No. AN44161A Package Code No. HSOP034-P-0300B Publication date: May 2012 Ver. AEB 1 AN44161A Contents Overview …………………………………………………………………………………………………………… 3
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AN44161A
HSOP034-P-0300B
AN44161A
vml25
HSOP034-P-0300B
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"Decoder IC"
Abstract: POCSAG S-29131A S-7040D S-7040DQP S-7040XQP
Text: Rev.1.1 S-7040D PAGING DECODER IC POCSAG The S-7040D decoder IC has been designed in accordance with the CCIR* Radio Paging Code Number 1 (POCSAG* code). The S-7040D can be used for display pager since It processes the POCSAG signal internally and sends the decoded data to an external microprocessor.
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S-7040D
S-7040D
"Decoder IC"
POCSAG
S-29131A
S-7040DQP
S-7040XQP
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BCH code
Abstract: No abstract text available
Text: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error cor rection, bit filling and synchronization schem e specified in IT U -T SS formerly CCITT recom m endation H.261. The forward error correcting code is a 2-error correcting BCH
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L64715
44-Pin
BCH code
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Untitled
Abstract: No abstract text available
Text: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error co r rection, bit filling and synchronization schem e specified in ITU-TSS formerly CCITT recom m endation H.261. The forw ard error correcting code is a 2-error correcting BCH
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L64715
511-bit
S3D4fi04
44-Pin
53Q4fl04
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Untitled
Abstract: No abstract text available
Text: Sw itches Product Selection Guide Model Description Circuitry Page Surface Mount CHS Slide DIP (4, 6, or 8 Position) CS-4 4 m m Sq. Selector S-7000 7 m m Sq. Coded SPST 1 Pole, 2 Position 2 Pole, 2 Position 1 Pole, 3 Position 10 Position, BCD 16 Position, BCH
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S-7000
SS-10
S-1000
S-2000
S-5000*
S-8000
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Untitled
Abstract: No abstract text available
Text: Switches Product Selection Guide Model Description Circuitry Page Surface Mount CHS Slide DIP (2, 4, 6, 8 or 10 Position) CS-4 4 mm Sq. Selector S-7000 7 mm Sq. Coded SPST 1 Pole, 2 Position 2 Pole, 2 Position 1 Pole, 3 Position 10 Position, BCD 16 Position, BCH
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S-7000
SS-10
S-1000
S-2000
S-5000*
S-8000
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Untitled
Abstract: No abstract text available
Text: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The L64715 implements the forw ard error co r rection, bit filling and synchronization scheme specified in CCITT Consultative Committee on International Telephones and Telegraphs recom m endation H.261. The forw ard error
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L64715
L64715
44-Pin
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PDF
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Untitled
Abstract: No abstract text available
Text: LSI LOGIC L64715 Two-Error Correcting BCH Encoder-Decoder Description The device can be programmed to operate w ith or w ithout bit filling. When the fill mode is selected, the first message bit is used to indi cate if the rest of the message has been filled
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L64715
511-bit
44-Pin
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Untitled
Abstract: No abstract text available
Text: HMP8364 S E M IC O N D U C T O R PRELIMINARY H.261 Video CODEC June 1997 Features Description • Complete and Fully Compliant H.261 Codec Including Framing and BCH Error Detect/Correct The Harris H.261 Video Codec is a single-chip, high perfor mance integrated circuit that simultaneously encodes and
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HMP8364
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Untitled
Abstract: No abstract text available
Text: HMP8364 S E M I C O N D U C T O R ADVANCE INFORMATION 9/26/96 H.261 Video Codec Features Description • Complete and fully compliant H.261 Codec including framing and BCH error detect/correct. The Harris H.261 Video Codec is a single-chip, high perfor mance integrated circuit that simultaneously encodes and
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HMP8364
HMP8364
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Untitled
Abstract: No abstract text available
Text: HMP8364 h a r r is S E M I C O N D U C T O R Ê Ê Ë W Ë È PRELIMINARY H.261 Video CODEC June 1997 Features Description • Com plete and Fully Com pliant H.261 Codec Including Framing and BCH Error Detect/Correct The Harris H.261 Video Codec is a single-chip, high perfor
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HMP8364
1-800-4-HARRIS
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S-7037A
Abstract: 7037a 5d3 transistor
Text: S-7037AF ► UNDER DEVELOPMENT PAGING DECODER IC POCSAG The S-7037AF decoder 1C is for use in the CCIR* Radio Paging Code Number 1 (POCSAG* code). It processes internally the POCSAG signals for the Tone-only pager. Furthermore, decoded data is transferred to an external
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S-7037AF
S-7037AF
S-7037A
S-2100)
S-1400)
SEGO-31
7037a
5d3 transistor
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Untitled
Abstract: No abstract text available
Text: Sw itches Product Selection G uide Model Description Circuitry Page Surface Mount CHS Slide DIP (2, 4, 6, 8 or 10 Position) CS-4 4 mm Sq. Selector SPST 1 Pole, 2 Position 44 46 2 Pole, 2 Position 1 Pole, 3 Position S-7000 7 mm Sq. Coded 10 Position, BCD
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S-7000
SS-10
S-1000
S-2000
S-5000*
S-8000
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s2913
Abstract: S-2913 S7038AF s7038
Text: S-7038AF PAGING DECODER IC POCSAG The S-7038A F decoder 1C is for use in the CCIR* Radio Paging Code Number 1 (POCSAG* code). It processes internally the POCSAG signals for the Tone-only pager. Furthermore, decoded data is transferred to an external microprocessor, so the S-7038AF can also be used for a
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S-7038AF
S-7038A
S-7038AF
SEGO-31
A123443
s2913
S-2913
S7038AF
s7038
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