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Catalog Datasheet	MFG & Type	PDF	Document Tags
MSL260G Abstract: MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB Text: Using the Intel 80960 CA with the PCI 9060 PCI evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000 0-15 Vendor ID, Allocated to PLX by PCI SIG (Read-only) (Default = 10B5)	Original	PDF	PCI9060 0x00000000 0x00000002 0x00000004 100ns 200ns 300ns 80960CA) PCLK1-33 MSL260G MSL-260-G D0806 R0807 T0803 D0802 D0807 RDD0804 D0808 5 pin reset ic ARB
PD0404 Abstract: U0401 U0403 pu0403 DIP10 16V8R LA29 LA30 I11I12 Text: 1 2 3 4 5 6 7 8 PCLK1B LA[2.31] A LA[2.31] LA3 LA28 LA29 LA30 LA31 RESET~ ADS~ BLAST~ WAIT~ READYO~ IORDY~ RESET~ ADS~ BLAST~ WAIT~ READYO~ PU0401 PD0401 1 2 3 4 5 6 7 8 9 10 11 14 23 13 U0401 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE IO1 IO2 IO3 IO4	Original	PDF	PU0401 PD0401 U0401 CS9060~ 20V8R PU0402 PU0403 PU0404 PD0402 PD0404 U0401 U0403 pu0403 DIP10 16V8R LA29 LA30 I11I12
D0807 Abstract: C0702 D0801 D0806 R0807 T0803 D0808 D0802 RDD0804 C0705 Text: PLX Technology PCI9060 Demo Board REV 1 1 2 3 4 5 6 7 8 9 10 11 Schematics 06/16/96 Title Page PCI9060, EEPROM 80960CA CPU Local Bus Control SRAM FLASH EPROM, UART 82596CA Ethernet Controller Ethernet Physical Layer PCI Bus Connector Reset, Test Headers Capacitors, Resistors	Original	PDF	PCI9060 PCI9060, 80960CA 82596CA U0101 20V8R U0102 PCI9060 D0807 C0702 D0801 D0806 R0807 T0803 D0808 D0802 RDD0804 C0705
16v8 book Abstract: BREQ9060 BREQ960 596CA Text: "* "Proprietary Rights Notice: "* * "This material contains the valuable proprietary and trade "secret information of PLX of Mountain View, California. "No part of such information	Original	PDF
1N4148/2 pin connector sip Abstract: ACT04 MOTOROLA 1N4148 D0805 pal programming sw dip-3 80960CA 15 pin through hole d sub connector 16v8h DIODE MOTOROLA B33 D0805 Text: Go to next Section: Using the Motorola 68040 Return to Table of Contents Using the Intel 80960 CA with the PCI 9060 PLX evaluation board, Schematics PLX TECHNOLOGY PCI9060 Demo Board I/O MAP 06/16/96 PCI Configuration Registers Address BIT Function 0x00000000	Original	PDF	PCI9060 0x00000000 0x00000002 0x00000004 100ns 200ns 300ns 80960CA) PCLK1-33 1N4148/2 pin connector sip ACT04 MOTOROLA 1N4148 D0805 pal programming sw dip-3 80960CA 15 pin through hole d sub connector 16v8h DIODE MOTOROLA B33 D0805
D0802 Abstract: D0807 C0702 16v8c T0803 D0806 R0807 D0808 RDD0804 pt3868 Text: 1 2 3 4 5 SPARE GATES: 1 2 3 4 5 6 7 8 9 10 11 14 23 13 A U0101 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 OE 1 2 3 4 5 6 7 8 9 10 11 14 23 13 22 21 20 19 18 17 16 15 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 20V8R DIP 9 U0102 CLK I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11	Original	PDF	U0101 20V8R U0102 PCI9060, 80960CA 82596CA PCI9060 PCI9060 D0802 D0807 C0702 16v8c T0803 D0806 R0807 D0808 RDD0804 pt3868
7705 reset Abstract: BREQ9060 BREQ960 h20000008 Text: "* "Proprietary Rights Notice: "* * "This material contains the valuable proprietary and trade "secret information of PLX of Mountain View, California. "No part of such information	Original	PDF
U0701 Abstract: C0702 C0704 La2 D22 D0701 U0702 c0706 D0702 C0708 C0705 Text: 1 LD[0.31] 2 3 LD[0.31] 4 5 6 7 8 LA[2.31] U0701 LD0 LD1 LD2 LD3 LD4 LD5 LD6 LD7 LD8 LD9 LD10 LD11 LD12 LD13 LD14 LD15 LD16 LD17 LD18 LD19 LD20 LD21 LD22 LD23 LD24 LD25 LD26 LD27 LD28 LD29 LD30 LD31 A B PU0701 PU0702 PU0703 PU0704 PCLK2A RESET CA PORT~	Original	PDF	U0701 PU0701 PU0702 PU0703 PU0704 BREQ596 PU0706 DS0702 R0702 R0703 U0701 C0702 C0704 La2 D22 D0701 U0702 c0706 D0702 C0708 C0705