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    BUFFER SCRAMBLER Search Results

    BUFFER SCRAMBLER Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    7UL2T125FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL2T126FK Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Buffer, SOT-765 (US8), -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    7UL1G07FU Toshiba Electronic Devices & Storage Corporation One-Gate Logic(L-MOS), Non-Inverter Buffer (Open Drain), USV, -40 to 85 degC Visit Toshiba Electronic Devices & Storage Corporation
    55501EJ Rochester Electronics LLC 55501 - Buffer/Driver Visit Rochester Electronics LLC Buy
    9621PC Rochester Electronics LLC 9621 - Buffer/Driver Visit Rochester Electronics LLC Buy

    BUFFER SCRAMBLER Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CMX878

    Abstract: Descrambler
    Text: Tx Output Buffer MOD Tx Level Control Scrambler Enable LOCAL ANALOGUE LOOPBACK Descrambler Enable Rx Gain Control + MODEM ENERGY DETECTOR CMX878 Block Diagram - BIAS RXIN RXFB Rx Input Amplifier


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    PDF CMX878 Descrambler

    Voice Activity Detector

    Abstract: PCM encoder VOICE SCRAMBLER activity diagram audio scrambler CMX649 encoder/decoder Scrambler Voice Detector pcm decoder
    Text: Mic. In ADM Encoder Buffer PCM Encoder Voice Activity Detector Programmable Anti-Alias Filter Input Level VDD Input Coded Signal VBIAS Scrambler Tx Data Encode VAD VSS Serial Clock Coding Algorithm Selections Transcoder C-BUS Serial I/O Control Registers Command Data


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    PDF CMX649 Voice Activity Detector PCM encoder VOICE SCRAMBLER activity diagram audio scrambler encoder/decoder Scrambler Voice Detector pcm decoder

    DIODE S4 72A

    Abstract: No abstract text available
    Text: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD 1.25V (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.8V TO 3.3V) FD_B Rev. B SIGNAL MONITOR 14 VIN+B VIN–B DDC ADC CORE BUFFER CONTROL REGISTERS V_1P0 SIGNAL MONITOR CLOCK GENERATION


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    PDF JESD204B AD9680 64-Lead AD9680-1000 AD9680-820 AD9680-500 AD9680-1000, DIODE S4 72A

    LAN89303

    Abstract: LAN89303AM 56-PIN AEC-Q100 obd connector ic 7432 encoder
    Text: LAN89303AM Three Port 10/100 Managed Ethernet Switch with MII/RMII for Automotive Applications PRODUCT FEATURES Datasheet — Programmable broadcast storm protection with global % control and enable per port — Programmable buffer usage limits — Dynamic queues on internal memory


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    PDF LAN89303AM D-76185 LAN89303 LAN89303AM 56-PIN AEC-Q100 obd connector ic 7432 encoder

    MA8121

    Abstract: AD10 AD11 MD10 MD11 MX98726
    Text: ADVANCED INFORMATION MX98726 SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE 1.0 Features • Support bus size configuration: - CPU : 8 bits, SRAM: 8 bits - CPU : 16 bits, SRAM: 8/16 bits • Flexible packet buffer partition and addressing space


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    PDF MX98726 July/28/1999 Dec/28/1999 Feb/14/2000 MA8121 AD10 AD11 MD10 MD11 MX98726

    MAR7

    Abstract: MD11 MD14 MX98726
    Text: ADVANCED INFORMATION MX98726 SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER WITH uP INTERFACE 1.0 Features • Support bus size configuration: - CPU : 8 bits, SRAM: 8 bits - CPU : 16 bits, SRAM: 8/16 bits • Flexible packet buffer partition and addressing space


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    PDF MX98726 July/28/1999 Dec/28/1999 Feb/14/2000 MAR7 MD11 MD14 MX98726

    LAN89303

    Abstract: LAN89303AM cd 8227 gp
    Text: LAN89303AM Three Port 10/100 Managed Ethernet Switch with MII/RMII for Automotive Applications PRODUCT FEATURES Datasheet — Programmable broadcast storm protection with global % control and enable per port — Programmable buffer usage limits — Dynamic queues on internal memory


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    PDF LAN89303AM LAN89303AM D-76185 LAN89303 cd 8227 gp

    micrel KS8995

    Abstract: KS8995 ks8995e YCL PH406466 802.1q trunk HB726-1 AT24C01A H1164 HB826-2 micrel mii
    Text: KS8995E Micrel KS8995E 5-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 1.10 On the media side, the KS8995E supports 10BaseT, 100BaseTX and 100BaseFX as specified by the IEEE 802.3 committee. Physical signal transmission and reception are enhanced


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    PDF KS8995E KS8995E 10BaseT, 100BaseTX 100BaseFX KS8995 micrel KS8995 YCL PH406466 802.1q trunk HB726-1 AT24C01A H1164 HB826-2 micrel mii

    558-5999-q9

    Abstract: PH406466 PACKAGE Delta LF8731 KS8999 factory test 5 port
    Text: KS8999 Micrel KS8999 Integrated 9-Port 10/100 Switch with PHY and Frame Buffer Rev. 1.14 KS8999 is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through I/O strapping or EEPROM programming at system reset


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    PDF KS8999 KS8999 10BaseT, 100BaseTX 100BaseFX 558-5999-q9 PH406466 PACKAGE Delta LF8731 KS8999 factory test 5 port

    KSZ8893MQL application note

    Abstract: KSZ8893MQL
    Text: KSZ8893MQL/MBL Integrated 3-Port 10/100 Managed Switch with PHYs Rev. 1.5 with patented mixed-signal low-power technology, three media access control MAC units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer


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    PDF KSZ8893MQL/MBL KSZ8893MQL/MBL, KSZ8893MQL/MBL M9999-121007-1 KSZ8893MQL application note KSZ8893MQL

    IP113

    Abstract: IP113A IP113-DS-P07 93C46 QFP-128L 30 PIN duplex led display
    Text: IP113 10/100 Base-Tx / Fx Converter Feature Utilize single clock source only 25Mhz 2 port 10/100 Ethernet switch with built in transceivers Utilize single power (2.5v) and memory 0.25um technology Build in SSRAM for frame buffer Packaged in 128 pin PQFP


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    PDF IP113 25Mhz) IEEE802 IP113 IP113-DS-P07 IP113A IP113-DS-P07 93C46 QFP-128L 30 PIN duplex led display

    KS8997

    Abstract: ksz8997 AT24C01A H1102 H1164 KS8995X 10BaseTX MICREL PQFP DATE CODE
    Text: KS8997/KSZ8997 8-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev 1.1 General Description The KS8997 contains eight 10/100 physical layer transceivers, eight MAC Media Access Control units with an integrated layer 2 switch. The device runs as


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    PDF KS8997/KSZ8997 KS8997 10BaseT 100BaseTX M9999-022807-1 ksz8997 AT24C01A H1102 H1164 KS8995X 10BaseTX MICREL PQFP DATE CODE

    Untitled

    Abstract: No abstract text available
    Text: FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD 1.25V (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V) BUFFER Rev. 0 DDC FD 4 SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± CONTROL REGISTERS V_1P0 FAST DETECT ÷2 ÷4 ÷8 AGND


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    PDF AD9690 JESD204B AD9690-1000EBZ AD9690-500EBZ 64-Lead AD9690-10002 AD9690-5002

    KSZ8893MQL application note

    Abstract: TLA-6T718 KSZ8893-MQL MDIO clause 45 specification KSZ8893 UPS052 KSZ8893 MII KSZ8893MQL KS8893MQLI KS8893MQL
    Text: KSZ8893MQL/MBL Integrated 3-Port 10/100 Managed Switch with PHYs Rev. 1.6 with patented mixed-signal low-power technology, three media access control MAC units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer


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    PDF KSZ8893MQL/MBL 10BASE-T 100BASETX. 100BASE-FX. KSZ8893MQL/MBL KS8893MQLI/MBLI KSZ8893 KSZ8893MQL/MBL, M9999-021110-1 KSZ8893MQL application note TLA-6T718 KSZ8893-MQL MDIO clause 45 specification UPS052 KSZ8893 MII KSZ8893MQL KS8893MQLI KS8893MQL

    KSZ8893MQL application note

    Abstract: "clock collision" KSZ8893MQL
    Text: KSZ8893MQL/MQLI Integrated 3-Port 10/100 Managed Switch with PHYs Rev. 1.3 with patented mixed-signal low-power technology, three media access control MAC units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer


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    PDF KSZ8893MQL/MQLI KSZ8893MQL, KSZ8893MQL M9999-061907-1 KSZ8893MQL application note "clock collision"

    KSZ8893-MQL

    Abstract: KS8893M MAG-JACK KSZ8893MQL application note KSZ8893 KSZ8893 MII TLA-6T718 KSZ8893MBL 10LINK LSE B3 transformer
    Text: KSZ8893MQL/MBL Integrated 3-Port 10/100 Managed Switch with PHYs Rev. 1.5 with patented mixed-signal low-power technology, three media access control MAC units, a highspeed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer


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    PDF KSZ8893MQL/MBL 10BASE-T 100BASETX. 100BASE-FX. KSZ8893MQL/MBL KS8893MQLI/MBLI KSZ8893 KSZ8893MQL/MBL, M9999-121007-1 KSZ8893-MQL KS8893M MAG-JACK KSZ8893MQL application note KSZ8893 MII TLA-6T718 KSZ8893MBL 10LINK LSE B3 transformer

    Untitled

    Abstract: No abstract text available
    Text: KS8997/KSZ8997 8-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev 1.1 General Description The KS8997 contains eight 10/100 physical layer transceivers, eight MAC Media Access Control units with an integrated layer 2 switch. The device runs as


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    PDF KS8997/KSZ8997 KS8997 10BaseT 100BaseTX M9999-022807-1

    RJ754-C-NL

    Abstract: 16Kx32 pulse h1012 HB614-1 KS8993 RJ754 reverse MII timing YCL Transformer PH406080 KSZ8993
    Text: KS8993 Micrel KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.06 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through


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    PDF KS8993 KS8993 10BaseT, 100BaseTX 100BaseFX KS899tomer. RJ754-C-NL 16Kx32 pulse h1012 HB614-1 RJ754 reverse MII timing YCL Transformer PH406080 KSZ8993

    IP175D

    Abstract: IP175 IP175 D IP175 datasheet 7 segment display duplex led type QFP-128L 14880 h60 buffer 93C46 05h12
    Text: IP175 5 Port 10/100 Ethernet Integrated Switch Feature Utilize single clock source only 25Mhz 5 port 10/100 Ethernet switch with built in transceivers Utilize single power (2.5v) and memory 0.25um technology Build in SSRAM for frame buffer Packaged in 128 pin PQFP


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    PDF IP175 25Mhz) IEEE802 IP175 IP175-DS-P05 IP175D IP175 D IP175 datasheet 7 segment display duplex led type QFP-128L 14880 h60 buffer 93C46 05h12

    Untitled

    Abstract: No abstract text available
    Text: MX98728AEC 1.0 Features GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION • 1.6KB TX FIFO to support maximum network throughput in the full duplex mode • 16/8 bits SRAM interface of the packet buffer supporting burst DMA for on-chip FIFOs


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    PDF MX98728AEC C9930 TA777001 38BAX

    KS8993

    Abstract: RJ754-C-NL KS8993I PV32 ycl 20pmt04 center tap transformer pulse h1012
    Text: KS8993 Micrel KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.04 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through


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    PDF KS8993 KS8993 10BaseT, 100BaseTX 100BaseFX KS899mer. RJ754-C-NL KS8993I PV32 ycl 20pmt04 center tap transformer pulse h1012

    MA17

    Abstract: MA18 MX98728EC Macronix marking GMAC
    Text: MX98728EC 1.0 Features GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION • 1.6KB TX FIFO to support maximum network throughput in the full duplex mode • 16/8 bits SRAM interface of the packet buffer supporting burst DMA for on-chip FIFOs


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    PDF MX98728EC C9930 TA777001 38BAX MA17 MA18 MX98728EC Macronix marking GMAC

    Untitled

    Abstract: No abstract text available
    Text: KS8993 Micrel KS8993 3-Port 10/100 Integrated Switch with PHY and Frame Buffer Rev. 2.06 The KS8993 has rich features such as VLAN and priority queuing and is designed to reside in an unmanaged design not requiring processor intervention. This is achieved through


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    PDF KS8993 KS8993 10BaseT, 100BaseTX 100BaseFX

    ssik212

    Abstract: SM 1159 design of scrambler and descrambler fsk modem 300
    Text: HARRIS SEflICOND 37E SECTOR 4302271 D 0Q21b7fl b IHAS Telecommunications Circuits CMOS Single-Chip 1200BPS MODEM CD22212 For Full-Duplex Operation over a Two-Wire Switched Telephone System A N T I­ ALIAS LPF DPSK MODULATOR SCRAM BLER BUFFER TxD - RxA FSK


    OCR Scan
    PDF 0Q21b7fl CD22212 1200BPS CD22212 80C51 ssik212 SM 1159 design of scrambler and descrambler fsk modem 300