SPRA821
Abstract: CCS addressable DSK6711 TMS320 TMS320C6211 TMS320C6711 XDS510 XDS560 RTDX RTDX start work
Text: Application Report SPRA821 – May 2002 How To Use High-Speed RTDX Effectively Doug Deao Software Development Systems ABSTRACT This application report familiarizes the reader with high-speed RTDX HSRTDX . It is assumed that the reader already has a working knowledge of RTDX. This application
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SPRA821
SPRA821
CCS addressable
DSK6711
TMS320
TMS320C6211
TMS320C6711
XDS510
XDS560
RTDX
RTDX start work
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diode T35 12H
Abstract: T35 12H DP83856 DP83840 DP83850 DP83856B SA10 SA11 SA12 SD14
Text: N DP83856B 100 Mb/s Repeater Information Base October 1997 General Description Features The DP83856B 100 Mb/s Repeater Information Base is designed specifically to meet the management demands of today's high speed Ethernet networking systems. • Supports up to 16 DP83850 Repeater Interface
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DP83856B
DP83850
100Mb
P83856B
diode T35 12H
T35 12H
DP83856
DP83840
SA10
SA11
SA12
SD14
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Untitled
Abstract: No abstract text available
Text: DP83856B DP83856B 100Mb/s Repeater Information Base Literature Number: SNLS029A N DP83856B 100 Mb/s Repeater Information Base October 1997 Features The DP83856B 100 Mb/s Repeater Information Base is designed specifically to meet the management demands of today's high speed
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DP83856B
DP83856B
100Mb/s
SNLS029A
DP83850s
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tms320tci6488 evm
Abstract: doorbell project amc MEZZANINE* tms320tci6488 hsmc connector TMS320TCI6488 AN599 C6000 EP2AGX125 tms320tci6488 evm rapidio
Text: Arria II GX RapidIO Interoperability with TI 6488 DSP Reference Design AN599-1.0 December 2009 Introduction The Altera RapidIO interoperability reference design provides a sample interface between the Altera RapidIO MegaCore® function configured on an Arria II GX device, and the Texas
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AN599-1
TMS320TCI6488
tms320tci6488 evm
doorbell project
amc MEZZANINE* tms320tci6488
hsmc connector
AN599
C6000
EP2AGX125
tms320tci6488 evm rapidio
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doorbell project
Abstract: TMS320TCI6482 C6000 TMS320TCI6482 EVM board Avalon DDR2
Text: RapidIO Interoperability with TI 6482 DSP Reference Design AN513-2.0 November 2008 Introduction The Altera RapidIO interoperability reference design provides a sample interface between the Altera RapidIO MegaCore® function and the Texas Instruments TMS320TCI6482
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AN513-2
TMS320TCI6482
doorbell project
TMS320TCI6482
C6000
TMS320TCI6482 EVM board
Avalon DDR2
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DSP2833x
Abstract: RTDX f28335 F28335 DSP281x DSP f28335 SPRA958H F2812 ADC RTDX projects rfid sprue02 DSP2833
Text: Application Report SPRA958H – September 2008 Running an Application from Internal Flash Memory on the TMS320F28xxx DSP David M. Alter DSP Applications - Semiconductor Group ABSTRACT Several special requirements exist for running an application from on-chip flash memory
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SPRA958H
TMS320F28xxx
DSP2833x
RTDX f28335
F28335
DSP281x
DSP f28335
SPRA958H
F2812 ADC RTDX
projects rfid
sprue02
DSP2833
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yb4 bridge diode
Abstract: national timer switch tb 179 Y81-Y8F CFC5 g1 rc16 EZOM SIEMENS BST t TB17 JT-G703 JT-G704
Text: MT9071 Quad T1/E1/J1 Transceiver Preliminary Information Features • • • • • • • • • DS5430 4 T1/E1/J1 framers and longhaul/shorthaul LIUs LIU sensitivity is 36dB in T1 and 40dB in E1 Internal reference switching PLL with holdover capability
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MT9071
DS5430
048Mbit/s
192Mbit/s
16-bit
MT9071
yb4 bridge diode
national timer switch tb 179
Y81-Y8F
CFC5
g1 rc16
EZOM
SIEMENS BST t
TB17
JT-G703
JT-G704
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C5502
Abstract: C6000 C6416 DM642 c5500
Text: Cache Analysis for Code Composer Studio] v2.3 User’s Guide SPRU575C April 2004 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any
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SPRU575C
C5502
C6000
C6416
DM642
c5500
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SPRA640
Abstract: TMS320C6000 0x00C0FFEE SPRU186E
Text: Application Report SPRA640 - March 2000 Programming and Debugging Tips for DSP/BIOS Don S. Gillespie Software Development Systems ABSTRACT DSP/BIOS provides the developers of DSP applications with a comprehensive set of tools for design and development of real time embedded applications. Due to the complexity and
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SPRA640
TMS320C6000
0x00C0FFEE
SPRU186E
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GR-820-CORE
Abstract: t7633 SLC96 ETS-300-011
Text: Product Brief May 1998 T7633 Dual T1/E1 3.3 V Short-Haul Terminator Features • Alarm reporting and performance monitoring per AT&T, ANSI, and ITU-T standards. The T7633 Dual T1/E1 Terminator consists of two independent, highly integrated, software-configurable, full-featured short-haul transceiver/framers.
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T7633
PN98-146TIC
GR-820-CORE
SLC96
ETS-300-011
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TS15E
Abstract: No abstract text available
Text: MT9072 Octal T1/E1/J1 Framer Advance Information DS5063 Features • • • • • • • Eight fully independent, T1/E1/J1 framers 3.3V supply with 5V tolerant inputs Selectable 2.048 Mbit/s or 8.192 Mbit/s serial buses for both data and signaling Framing Modes:
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MT9072
IEEE-1149
DS5063
MT9072AB
MT9072AV
MT9072
TS15E
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TS15E
Abstract: E1210 TS127 08 Y2C diode mark JT-G703 JT-G704 JT-G706 MT9072 MT9072AB MT9072AV
Text: Zarlink Semiconductor; formerly know as Mitel Semiconductor, announced its name and new identity May 29, 2001. To reflect that new identity, rebranding of all product documentation will be completed by August 31, 2001. Mitel, M Mitel and other "Mitel" licensed marks are owned by Mitel Networks Corporation
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MT9072
DS5063
TS15E
E1210
TS127 08
Y2C diode mark
JT-G703
JT-G704
JT-G706
MT9072
MT9072AB
MT9072AV
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PCM24
Abstract: No abstract text available
Text: MT9072 Octal T1/E1/J1 Framer Data Sheet Features • • • • • • • August 2011 Eight fully independent, T1/E1/J1 framers 3.3 V supply with 5 V tolerant inputs Selectable 2.048 Mbit/s or 8.192 Mbit/s serial buses for both data and signaling Framing Modes:
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MT9072
IEEE-1149
MT9072AV
MT9072AV2
PCM24
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E1166
Abstract: SA8F FEI 30
Text: MT9072 Octal T1/E1/J1 Framer Data Sheet Features • • • • • • • DS5063 Eight fully independent, T1/E1/J1 framers 3.3V supply with 5V tolerant inputs Selectable 2.048 Mbit/s or 8.192 Mbit/s serial buses for both data and signaling Framing Modes:
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MT9072
IEEE-1149
DS5063
MT9072AB
MT9072AV
MT9072
E1166
SA8F
FEI 30
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D8172
Abstract: TS15E TS16E cyclic redundancy check e1166
Text: MT9072 Octal T1/E1/J1 Framer Data Sheet Features • • • • • • • DS5063 Eight fully independent, T1/E1/J1 framers 3.3V supply with 5V tolerant inputs Selectable 2.048 Mbit/s or 8.192 Mbit/s serial buses for both data and signaling Framing Modes:
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MT9072
IEEE-1149
DS5063
MT9072AB208
MT9072AV220
MT9072
D8172
TS15E
TS16E
cyclic redundancy check
e1166
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ja 16202
Abstract: No abstract text available
Text: MT9072 Octal T1/E1/J1 Framer Data Sheet Features • • • • • • • DS5063 Eight fully independent, T1/E1/J1 framers 3.3V supply with 5V tolerant inputs Selectable 2.048 Mbit/s or 8.192 Mbit/s serial buses for both data and signaling Framing Modes:
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MT9072
IEEE-1149
DS5063
MT9072AB
MT9072AV
MT9072
ja 16202
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program MCF51QE128 using code warrior v10
Abstract: LCD ccs compiler tutorial CodeWarrior and MCF51QE128 HCS08 SPI code example assembly B09121 PIC PROJECT CCS C Freescale usb mcf51jm128 driving LCD in ccs compiler hcs08 linker map rs08 SCI c code
Text: DRAFT CodeWarrior Development Studio for Microcontrollers V10.x Targeting Manual Revised: January 21, 2010 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. CodeWarrior is a trademark or registered trademark of Freescale Semiconductor, Inc. in the United States and/or other countries. PROCESSOR EXPERT
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HCS08
program MCF51QE128 using code warrior v10
LCD ccs compiler tutorial
CodeWarrior and MCF51QE128
HCS08 SPI code example assembly
B09121
PIC PROJECT CCS C
Freescale usb mcf51jm128
driving LCD in ccs compiler
hcs08 linker map
rs08 SCI c code
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Untitled
Abstract: No abstract text available
Text: LF3347 D E V IC E S IN C O R P O R A T E D High-Speed Image Filter with Coefficient RAM FEATURES □ 83 MHz Data Input and Compu tation Rate □ Four 12 x 12-bit Multipliers with Individual Data and Coefficient Inputs □ Four 256 x 12-bit Coefficient Banks
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OCR Scan
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LF3347
12-bit
32-bit
16-bit
120-pin
LF3347
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mxt 211
Abstract: signalling and frame alignment in E1 G704 SLC96 alarm frame format b30 c300 - 1 tsr1-24
Text: 29C96 MATRA MHS T1-DS1/E1-CEPT Framer Formatter Description The 29C96 is a programmable CMOS device interfacing with T1-DS1 or E1-CEPT transceivers. The 29C96 supports following frame formats : D DS1 : 4 frames DMI , D4 (G704), ESF (G704), SLC-96 (DMI), DDS (DMI)
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29C96
29C96
SLC-96
29C94
mxt 211
signalling and frame alignment in E1
G704
SLC96 alarm frame format
b30 c300 - 1
tsr1-24
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PIC18f452 frequency counter
Abstract: usart C18 CODE PIC18XXXX USART PIC applications PIC16XXXX DS30475 PIC18f452 timer0 codes PIC18F452 timer0 DS39026 ds39500
Text: PIC18XXXX Microcontroller Family Product Information The PIC18XXXX microcontroller family provides PICmicro devices in 8- to 84-pin packages, that are both socket and software upwardly compatible to the PIC16XXXX family. The PIC18XXXX family includes all the popular peripherals, such as MSSP, ESCI,
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PIC18XXXX
84-pin
PIC16XXXX
PIC18XXXX
16-bit
10-bit
DS30327A
PIC18f452 frequency counter
usart C18 CODE
USART PIC applications
DS30475
PIC18f452 timer0 codes
PIC18F452 timer0
DS39026
ds39500
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Dh-19
Abstract: ISP1562 ptc circuit controller 24C01 2A01 ISP1562BE LQFP100
Text: ISP1562 Hi-Speed USB PCI host controller Rev. 04 — 6 August 2009 Product data sheet 1. General description The ISP1562 is a Peripheral Component Interconnect PCI -based, single-chip Universal Serial Bus (USB) host controller. It integrates two Original USB Open Host Controller
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ISP1562
ISP1562
Dh-19
ptc circuit controller
24C01
2A01
ISP1562BE
LQFP100
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Untitled
Abstract: No abstract text available
Text: DP8344B Biphase Communications Processor Features Transceiver Y Software configurable for 3270 3299 5250 and general 8-bit protocols Y Fully registered status and control Y On-chip analog line receiver Processor Y 20 MHz clock 50 ns T-states Y Max instruction cycle 200 ns
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DP8344B
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dw2 18- 2 5t
Abstract: Schematics 5250 DP8342 ST 9336 F933 BCP63 AN-499 DP8343 HP1651A C1995
Text: DP8344B Biphase Communications Processor General Description although a TTL-level serial input is also provided for applications where an external comparator is preferred A typical system is shown below Both coax and twinax line interfaces are shown as well as an example of the optional remote processor interface
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DP8344B
dw2 18- 2 5t
Schematics 5250
DP8342
ST 9336
F933
BCP63
AN-499
DP8343
HP1651A
C1995
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1BH62
Abstract: 5721-1 MO-112 MT9075B MT9075BL MT9075BP PCM30 PE-64934 PE-65351
Text: MT9075B E1 Single Chip Transceiver Preliminary Information Features • • The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for Sa bits and channel 16. The LIU interfaces the framer functions to the PCM
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MT9075B
MT9075B
1BH62
5721-1
MO-112
MT9075BL
MT9075BP
PCM30
PE-64934
PE-65351
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