CLOCK MANAGEMENT Search Results

CLOCK MANAGEMENT Result Highlights (5)

Part	Manufacturer	Description
TB67S539FTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=2/Clock Interface
TB67S149AFTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Unipolar Type/Vout(V)=84/Iout(A)=3/Clock Interface
TB67S549FTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver/Bipolar Type/Vout(V)=40/Iout(A)=1.5/Clock Interface
TB67S589FTG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / VQFN32
TB67S589FNG	Toshiba Electronic Devices & Storage Corporation	Stepping Motor Driver / Bipolar Type / Vout(V)=50 / Iout(A)=3.0 / CLK input type / HTSSOP28

CLOCK MANAGEMENT Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
49fct3805a Abstract: 40 MHZ OSCILLATOR 49FCT805CT 5v927 74FCT88915TT70 74FCT3807D oscillator 2.048 mhz 5T9306 49FCT805BT 32 MHZ OSCILLATOR Text: IDT Clock Management PRODUCT FAMILY and the new LVDS clock fanout family, as well as the IDT Precision and Stratum WAN PLL clock generators. Advanced Clock Management — On Time, All the Time The IDT comprehensive portfolio of Clock Management products enhances time to	Original	1-04/EM/LMN/HOP/5K FLYR-TIME-00014 49fct3805a 40 MHZ OSCILLATOR 49FCT805CT 5v927 74FCT88915TT70 74FCT3807D oscillator 2.048 mhz 5T9306 49FCT805BT 32 MHZ OSCILLATOR	PDF
automatic change over switch circuit diagram Abstract: linear handbook clock chip differential ring oscillator led using clock circuit diagram with AGX52005-1 SSTL-18 SPREAD-SPECTRUM SYSTEM Text: Section II. Clock Management This section provides information on clock management in Arria GX devices. It describes the enhanced and fast phase-locked loops PLLs that support clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces.	Original		PDF
linear handbook Abstract: SSTL-18 AGX52005-1 Text: Section II. Clock Management This section provides information on clock management in Arria GX devices. It describes the enhanced and fast phase-locked loops PLLs that support clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces.	Original		PDF
EP1S60 Abstract: SPREAD-SPECTRUM SYSTEM Text: Section II. Clock Management This section provides information on clock management in Stratix GX devices. It describes the enhanced and fast phase-locked loops PLLs that support clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces.	Original		PDF
automatic change over switch circuit diagram Abstract: EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 Text: Section II. Clock Management This section provides information on clock management in Stratix II GX devices. It describes the enhanced and fast phase-locked loops PLLs that support clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces.	Original		PDF
automatic change over switch circuit diagram Abstract: EP2S15 EP2S180 EP2S30 EP2S60 EP2S90 gx 743 Text: Section II. Clock Management This section provides information on clock management in Stratix II GX devices. It describes the enhanced and fast phase-locked loops PLLs that support clock management and synthesis for on-chip clock management, external system clock management, and high-speed I/O interfaces.	Original		PDF
vhdl code for phase frequency detector Abstract: vhdl code for DCM CLKFX180 dcm verilog code Text: R Using Digital Clock Managers DCMs Overview Virtex-II devices have 4 to 12 DCMs, and each DCM provides a wide range of powerful clock management features: • Clock De-skew: The DCM contains a digitally-controlled feedback circuit (delaylocked loop) that can completely eliminate clock distribution delays. Clock de-skew	Original	UG002 clk90 CLK90 clkfx180 CLKFX180 vhdl code for phase frequency detector vhdl code for DCM dcm verilog code	PDF
vhdl code for phase frequency detector Abstract: vhdl code for multiplexer 64 to 1 using 8 to 1 vhdl code for DCM vhdl code for Digital DLL Text: R Chapter 2: Design Considerations Digital Clock Managers DCMs Overview Virtex-II Pro devices have four to eight DCMs, and each DCM provides a wide range of powerful clock management features: • Clock De-skew: The DCM contains a digitally-controlled feedback circuit (delaylocked loop) that can completely eliminate clock distribution delays. Clock de-skew	Original	UG012 vhdl code for phase frequency detector vhdl code for multiplexer 64 to 1 using 8 to 1 vhdl code for DCM vhdl code for Digital DLL	PDF
10KW Abstract: No abstract text available Text: CY24260 Clock Generator for PDA/MP3/LCD Features Table 1. Frequency Table • • • • Supports PDA and Web-Pad clocking requirements Audio Clock for hardware codec or for AC 97 codec LCD controller programmable clock Advanced power management with synchronous clock	Original	CY24260 20-lead CY24260 10KW	PDF
Untitled Abstract: No abstract text available Text: Clock & Timing IC Solutions www.hittite.com REF PLL CLK1 CLK2 CLOCK MANAGEMENT CLKN Hittite has developed an industr y-leading line of high per formance clock distribution and clock generation products that enable the system designer to maximize the performance from data converters and physical layer PHY	Original	CT-0313	PDF
CLK32 Abstract: EVK-SH3000USB SH3000 SH3000EK SH3001 SH3001IMLTR pseudo-random noise generator Text: SH3001 MicroBuddy Real-Time Clock and Clock Management Support IC for Microcontrollers SYSTEM MANAGEMENT Description Features The programmable SH3001 MicroBuddy™ µBuddy™ provides mandatory microcontroller support functions: ¨ ¨ Clock Management System	Original	SH3001 SH3001, CLK32 EVK-SH3000USB SH3000 SH3000EK SH3001IMLTR pseudo-random noise generator	PDF
SH3001IMLTRT Abstract: pseudo-random noise generator Text: SH3001 MicroBuddy Real-Time Clock and Clock Management Support IC for Microcontrollers SYSTEM MANAGEMENT Description Features The programmable SH3001 MicroBuddy™ µBuddy™ provides mandatory microcontroller support functions: ♦ ♦ Clock Management System	Original	SH3001 SH3001, SH3001IMLTRT pseudo-random noise generator	PDF
pseudo-random noise generator Abstract: CLK32 EVK-SH3000USB SH3000 SH3000EK SH3001 SH3001IMLTR SH3001IMLTRT Text: SH3001 MicroBuddy Real-Time Clock and Clock Management Support IC for Microcontrollers SYSTEM MANAGEMENT Description Features The programmable SH3001 MicroBuddy™ µBuddy™ provides mandatory microcontroller support functions: ♦ ♦ Clock Management System	Original	SH3001 SH3001, pseudo-random noise generator CLK32 EVK-SH3000USB SH3000 SH3000EK SH3001IMLTR SH3001IMLTRT	PDF
Untitled Abstract: No abstract text available Text: SH3001 MicroBuddy Real-Time Clock and Clock Management Support IC for Microcontrollers SYSTEM MANAGEMENT PRELIMINARY Description Features The programmable SH3001 MicroBuddy™ µBuddy™ provides mandatory microcontroller support functions: ¨ ¨ Clock Management System	Original	SH3001 SH3001,	PDF

semi catalog Abstract: j510 Motorola transistor smd marking codes rf choke cross comparison books TTL catalog IC Data-book MPC930 MPC9449 MPC951 MPC952 Text: Freescale Semiconductor Data Book. Advanced Clock Drivers. DL207 Rev. 2 8/2004 Advanced Clock Drivers Selector Guide 1 Clock Generator Data Sheets 2 QUICCClock Generator Data Sheets 3 Failover or Redundant Clock Data Sheets 4 Clock Synthesizer Data Sheets	Original	DL207 xx/2004 semi catalog j510 Motorola transistor smd marking codes rf choke cross comparison books TTL catalog IC Data-book MPC930 MPC9449 MPC951 MPC952	PDF
2105 8PIN SOIC Abstract: bascom Text: PCS1P2192A June 2009 rev 1.0 VDP Multiple Pixel Clock Generator Product Description Features • Generates multiple clock outputs from 20MHz The PCS1P2192A is a clock generator that generates external reference clock multiple selectable pixel clock outputs for Video Display	Original	PCS1P2192A 20MHz PCS1P2192A 20MHz 108MHz, 27MHz, 85MHz, 65MHz, 25MHz, 2105 8PIN SOIC bascom	PDF
Untitled Abstract: No abstract text available Text: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable http://onsemi.com Description The NB100LVEP224 is a low skew 1-to-24 differential clock driver, designed with clock distribution in mind, accepting two clock	Original	NB100LVEP224 NB100LVEP224 1-to-24 NB100LVEP224/D	PDF
CLKFX180 Abstract: CLK2X180 Text: Applications Clock Management The Virtex-II DCM – Digital Clock Manager Higher system bandwidth requires higher data rates between devices, and advanced clock management. 24 Xcell Journal by Maria George Product Applications Engineer, Xilinx Inc. [email protected]	Original	Period/256 CY7B9911V 32-pin CLKFX180 CLK2X180	PDF
405C Abstract: LVEP224 NB100LVEP224 Socket IC 80 pin LQFP Text: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable http://onsemi.com Description The NB100LVEP224 is a low skew 1−to−24 differential clock driver, designed with clock distribution in mind, accepting two clock	Original	NB100LVEP224 NB100LVEP224 1-to-24 NB100LVEP224/D 405C LVEP224 Socket IC 80 pin LQFP	PDF
LQFP-64 thermal pad Abstract: No abstract text available Text: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable http://onsemi.com Description The NB100LVEP224 is a low skew 1−to−24 differential clock driver, designed with clock distribution in mind, accepting two clock	Original	NB100LVEP224 1-to-24 NB100LVEP224/D LQFP-64 thermal pad	PDF
EP1C12 Abstract: No abstract text available Text: 6. Using PLLs in Cyclone Devices C51006-1.5 Introduction Cyclone FPGAs offer phase locked loops PLLs and a global clock network for clock management solutions. Cyclone PLLs offer clock multiplication and division, phase shifting, programmable duty cycle,	Original	C51006-1 EP1C12	PDF
CK97 Abstract: PCK2000 PCK2000M PCK2001 PCK2001M Text: PCK2000 CK97 System Clock Generator PCK2001 14.318-150 MHz 1:18 Clock Buffer Description The PCK2000 is a CK97 system clock generator that synthesizes 66/100 MHz single-ended clock frequencies. The PCK2001 is a 1:18 clock buffer that fans out these clock frequencies to the system's dual in-line memory modules	Original	PCK2000 PCK2001 PCK2000 PCK2001 241609/7K/FP/2pp/0799 CK97 PCK2000M PCK2001M	PDF
W130 Abstract: PCI17 Text: PRELIMINARY W130 Spread Spectrum Desktop/Notebook System Clock Features CPU0:5 Clock Skew: .175 ps • Maximized EMI suppression using Cypress’s Spread Spectrum technology • Six copies of CPU Clock • Eight copies of PCI Clock synchronous w/CPU clock	Original	318-MHz 48-MHz 100-MHz 66-MHz W130 PCI17	PDF
LQFP-64 datasheet Abstract: LQFP-64 LVEP224 NB100LVEP224 Text: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable http://onsemi.com Description The NB100LVEP224 is a low skew 1-to-24 differential clock driver, designed with clock distribution in mind, accepting two clock	Original	NB100LVEP224 NB100LVEP224 1-to-24 NB100LVEP224/D LQFP-64 datasheet LQFP-64 LVEP224	PDF

CLOCK MANAGEMENT Search Results

CLOCK MANAGEMENT Result Highlights (5)

CLOCK MANAGEMENT Datasheets Context Search

49fct3805a

automatic change over switch circuit diagram

linear handbook

EP1S60

automatic change over switch circuit diagram

automatic change over switch circuit diagram

vhdl code for phase frequency detector

vhdl code for phase frequency detector

10KW

Untitled

CLK32

SH3001IMLTRT

pseudo-random noise generator

Untitled

semi catalog

2105 8PIN SOIC

Untitled

CLKFX180

405C

LQFP-64 thermal pad

EP1C12

CK97

W130

LQFP-64 datasheet