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    525R-02LF Renesas Electronics Corporation OSCAR™ User Configurable Clock Visit Renesas Electronics Corporation
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    525R-11LF Renesas Electronics Corporation User Configurable Clock Visit Renesas Electronics Corporation
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    PEPPERL+FUCHS GmbH CAN-USB-CONFIGURATION-KIT

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    CONFIGURATION Datasheets (15)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    Configuration Altera Altera Programming Hardware Data Sheet Original PDF
    Configuration Altera AN 33: Configuring FLEX 8000 Devices Original PDF
    Configuration Altera ByteBlasterMV Parallel Port Download Cable Data Sheet Original PDF
    Configuration Altera Figure 43 Design File for Configuring FLEX 10K & FLEX 6000 (37 KB) Original PDF
    Configuration Altera Sharp LHF16J061 Data Sheet Original PDF
    Configuration Altera Figure 43 Design File for Configuring APEX 20K (43 KB) Original PDF
    Configuration Altera ByteBlaster Parallel Port Download Cable Data Sheet Original PDF
    Configuration Altera AN 116: Configuring SRAM-Based LUT Devices Original PDF
    Configuration Altera AN 38: Configuring Multiple FLEX 8000 Devices Original PDF
    Configuration Altera AN 122: Using Jam STAPL for ISP & ICR via an Embedded Processor Original PDF
    Configuration Altera EPC16 Configuration Device Data Sheet Original PDF
    Configuration Altera Altera Device Package Information Data Sheet Original PDF
    Configuration Altera Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet Original PDF
    Configuration Altera MasterBlaster Serial-USB Communications Cable Data Sheet Original PDF
    Configuration Altera Configuring PLDs with FLASH Memory Original PDF

    CONFIGURATION Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    Untitled

    Abstract: No abstract text available
    Text: DTC143 TM/TE/TUA/TCA/TSA NPN Small Signal Transistor Small Signal Diode Features —Built-in bias resistors enable the configuration of an inverter circuit without connecting external input resistor see equivalent circuit . —The bias resistors consist of thin -film resistors with


    Original     		DTC143 OT-723 OT-523 OT-323 OT-23 O-92S PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11032, 74AC11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES TI0060— D2957, JULY 1987— REVISED MARCH 1990 54A C 11032 . . . J PACKAGE 74A C 11032 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin V c c and GND Configurations to


    OCR Scan     		54AC11032, 74AC11032 TI0060-- D2957, 500-mA 300-mil 54AC11032 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D2957. JULY 1987 - REVISED APRIL 1993 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations


    OCR Scan     		54AC11021 74AC11021 D2957. 500-mA 300-mll PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11002, 74AC11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES D2957, JUNE 1987 - REVISED APRIL 1993 54AC11002 . . . J PACKAGE 74AC11002 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Configuration Minimizes High-Speed Switching Noise


    OCR Scan     		54AC11002, 74AC11002 D2957, 500-mA 300-mil 54AC11002 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise


    OCR Scan     		54ACT11002 74ACT11002 SCAS003A D2957, 500-mA 300-mll PDF

    D2957

    Abstract: No abstract text available
    Text: 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS I_ • ■ I I I D2957, JULY 1987-R E V IS E D APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations


    OCR Scan     		500-mA 300-mll AC11240 AC11244, D2957 PDF

    74AC11520

    Abstract: No abstract text available
    Text: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations


    OCR Scan     		54AC11520 74AC11520 D2957, 500-mA 300-mil 54AC11520 74AC11S20. PDF

    2a117

    Abstract: No abstract text available
    Text: 54AC11158, 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS TI010&— D 2957 JULY 1969— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11158 . . . J PACKAGE 74AC11158 . . . DW OR N PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to


    OCR Scan     		54AC11158, 74AC11158 TI010 500-mA 300-mil 54AC11158 74AC11158 2a117 PDF

    2N404

    Abstract: MPS404 2n404a a5t404
    Text: TYPES A5T404, A5T404A, A8T404, A8T404A P-N-P SILICON TRANSISTORS _B U L L E T I N N O . O L -S 7 3 1 1 9 7 9 , M A R C H 1973 SILECTt TRANSISTORS* FOR LOW-COST REPLACEMENT OF GERMANIUM 2N404, 2N404A • A5T404, A5T404A Have Standard TO-18 100-mil Pin-Circle Configuration


    OCR Scan     		A5T404, A5T404A, A8T404, A8T404A 2N404, 2N404A A5T404A 100-mil 2N404 MPS404 2n404a a5t404 PDF

    Untitled

    Abstract: No abstract text available
    Text: 74ACT11132 QUADRUPLE POSITIVE-NAND GATE WITH SCHMITT-TRIGGER INPUTS SCAS177 - D3974, JANUARY 1992 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Center-Pin V^c and GND Pin Configurations Minimize High-Speed Switching Noise EP/C Enhanced-Performance Implanted


    OCR Scan     		74ACT11132 SCAS177 D3974, 500-mA 300-mll foCAS177 PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC 11004, 74AC11004 HEX INVERTERS TI0044— D2957, FEBRUARY 1068— REVISED M ARCH 1990 54AC11004 . . . J PACKAGE 74AC11004 . . . DW OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin Vq c and GND Configurations to


    OCR Scan     		74AC11004 TI0044-- D2957, 500-mA 300-mil 54AC11004 74AC11004 PDF

    TLP570

    Abstract: tlp371
    Text: F7 Typa No. Pin Configuration TLP371 TLP372 Features CTR % eiF Min. im A l V c e c d (V) Safety Standard (Note 2) (V) BVs (Vrms) 100 300 5,000 O 1.2 100 35 2,500 o 1.2 100 300 5,000 o eie Max. (mA) 1,000 1.2 1,000 1,000 VCEO UL TClV VDE BSI High V ceo (300V)


    OCR Scan     		TLP371 TLP372 TLP570 TLP571 TLP627 TLP627-2 TLP627-3 TLP627-4 TLP570 tlp371 PDF

    TI009

    Abstract: No abstract text available
    Text: 54AC11643, 74AC 11643 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0095— D2957, JU LY 1987— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11643 . . . JT PACKAGE 74AC11643 . . . DW OR NT PACKAGE TOP VIEW Center-Pin V c c and GND Configurations to


    OCR Scan     		54AC11643, I0095-- D2957, 500-mA 300-mil 54AC11643 74AC11643 TI009 PDF

    D2957

    Abstract: 1987-REVISEDAPRIL
    Text: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted


    OCR Scan     		54ACT11030 74ACT11030 D2957. 1987-REVISEDAPRIL 500-mA 300-mll D2957, D2957 PDF

    Untitled

    Abstract: No abstract text available
    Text: PAL20L8A, PAL20R4A, PAL20R6A, PAL20R8A STANDARD HIGH-SPEED PAL CIRCUITS D 2 7 0 6 , DEC EM BE R 1 9 8 2 - R E V IS E D DEC EM BE R 1 9 8 7 PAL20L8' M SUFFIX . . . JW PACKAGE C SUFFIX . . . JW OR NT PACKAGE Standard High Speed 25 ns PAL Family • Choice of Input/Output Configuration


    OCR Scan     		PAL20L8A, PAL20R4A, PAL20R6A, PAL20R8A 300-mil 600-mil 13-state PAL20L8' AL20L8A PDF

    74690

    Abstract: 74692 8Q21
    Text: TFyAi TNSTR LOGIC T EX A S I N S T R { L O G I C ! 1 1 91D 74690 D T-5£-0? D E | 0 ^ 1 7 2 3 DD74h1G 5 1 ~ SN 74 A S 18 2 3 9-BIT BUS INTER FA CE FLIP-FLUPS WITH 3-STATE OUTPUTS APRIL 1 9 8 7 NT PACKAGE Center V q c ar|d GND Configuration Provides Minimum Lead Inductance in High


    OCR Scan     		DD74h1G AS823 SN74AS1823 0074bT3 SDAS126 74690 74692 8Q21 PDF

    sn74as306

    Abstract: No abstract text available
    Text: SN74AS305 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER D3SM, JUNE 1990 - REVISED SEPTEMBER 1990 Maximum Output Skew of 1 ns D OR N PACKAGE {TOP VIEW Maximum Pulse Skew of 1 n* 03 [ Center Pin Vcc and GND Configurations Minimize High-Speed Switching Noise U 04 [ 2


    OCR Scan     		SN74AS305 300-mil sn74as306 PDF

    Untitled

    Abstract: No abstract text available
    Text: TOSHIBA TC4W53F/FU TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4W53F, TC4W53FU 2-CHANNEL MULTIPLEXER / DEMALTIPLEXER The TC4W53 is multiplexer with capabilities of selection and mixture of analog signal and digital signal. TC4W53F has 2 channel configuration.


    OCR Scan     		TC4W53F/FU TC4W53F, TC4W53FU TC4W53 TC4W53F 20og1 20ogig- -50dB PDF

    Untitled

    Abstract: No abstract text available
    Text: SN74AS305 OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER D3596, JUNE 1990 D OR N PACKAGE CTOP VIEW Maximum Output Skew of 1 ns Maximum Pulse Skew of 1 ns Center Pin Vc c and GND Configurations Minimize High-Speed Switching Noise Package Options Include Plastic “Small


    OCR Scan     		SN74AS305 D3596, 300-mil PDF

    PD4A

    Abstract: No abstract text available
    Text: _ bq3285 UIMITRODE- Real-Time Clock RTC Features >• Direct clock/calendar replace­ ment for IBM AT-compatible computers and other applications >- Functionally compatible with the DS1285 ~ Closely matches MC146818A pin configuration >• 114 bytes of general nonvolatile


    OCR Scan     		bq3285 24-hour 24-pin DS1285 MC146818A bq3285 PD4A PDF

    Untitled

    Abstract: No abstract text available
    Text: GaA«As IRED a PHOTO-IC 6N138,139 6N138 CURRENT LOOP DRIVER. U n it in mm LO W INPUT CURRENT LINE RECEIVER. C M O S LOGIC INTERFACE. The T O S H IB A 6N138 and 6N139 consists of a G a A fA s infrared em itting diode coupled w ith a split-Darlington output configuration.


    OCR Scan     		6N138 6N138) 6N138 6N139 2500Vrms 6N139 10//s 35/iS PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11020,74AC11020 DUAL 4-INPUT POSITIVE-NAND GATES D2957, MAHCH 1987-REVISEDAPRIL1993 54AC11020. . . J PACKAGE 74AC11020. . . D OR N PACKAGE TOP VIEW * Flow-Through Architecture Optimizes PCB Layout * Center-Pin Vcc and GND Configurations Minimize High-Speed Switching Noise


    OCR Scan     		54AC11020 74AC11020 D2957, 1987-REVISEDAPRIL1993 500-mA 300-mil PDF

    Untitled

    Abstract: No abstract text available
    Text: MOS LSI T M S 3133 NC 1024-BIT STATIC SHIFT REGISTER B U L L E T I N N O . D L -S 7 5 1 2 2 6 4 , M A Y 1 9 7 5 DC to 2-MHz Operation 8-PIN P LASTIC D U A L -IN -L IN E PACKAG E TOP V IE W S tatic Configuration Single TTL-C om patible Clock Inputs and O utputs F u lly T TL-C om patible


    OCR Scan     		1024-BIT PDF

    Untitled

    Abstract: No abstract text available
    Text: 54AC11030, 74AC11030 8-INPUT POSITIVE-NAND GATES D2957. JUNE 1987-R E V IS E D APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-Pin Vqc and GND Configurations Minimize High-Speed Switching Noise EPIC'“ Enhanced-Pertormance Implanted CMOS 1-^m Process


    OCR Scan     		54AC11030, 74AC11030 D2957. 1987-R 500-mA 300-mll S4AC11032-85 54AC11030 D2957, PDF