PP155
Abstract: No abstract text available
Text: PPP Packet Processor 155 Mbps MegaCore Function PP155 August 2001; ver. 1.01 Data Sheet • ■ ■ ■ ■ ■ ■ ■ Features ■ ■ Typical Applications Full-duplex processing capability Octet-synchronous mode operation High-level data link control (HDLC)-type framing
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PP155)
32-bit
PP155
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PLSM-PP622
Abstract: PP622 STS12CFRM
Text: PPP Packet Processor 622 Mbps MegaCore Function PP622 August 2001; ver. 1.01 Data Sheet • ■ ■ ■ ■ ■ ■ ■ Features ■ ■ Typical Applications Full-duplex processing capability Octet-synchronous mode operation High-level data link control (HDLC)-type framing
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PP622)
32-bit
PLSM-PP622
PP622
STS12CFRM
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stk 3120
Abstract: 80c186 obsolete date CR056 DT 8210 IC TSC 232 CPE cr038 DT 8210 stk 432 070 BT8210EPF 8210 microprocessor
Text: Advance Information This document contains information on a product under development. The parametric information contains target parameters that are subject to change. Printed exclusively for DataRace Bt8209/8210 SMDS Control and Reassembly Formatter SCARF
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Bt8209/8210
Bt8209
Bt8210
stk 3120
80c186 obsolete date
CR056
DT 8210 IC
TSC 232 CPE
cr038
DT 8210
stk 432 070
BT8210EPF
8210 microprocessor
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N8222
Abstract: 28-22-21 bt8222
Text: Bt8222 ATM Transmitter/Receiver with UTOPIA Interface The Bt8222 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
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Bt8222
Bt8222
TR-TSV-000772,
TR-TSV-000773,
TR-NWT-000253,
T1S1/92-185;
N8222
28-22-21
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n8223
Abstract: N-822 CN8223EPF AD6116 78P7200 CN8223 BT8222EPFE PROCESS CONTROL TIMER using 555 ic
Text: CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
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CN8223
CN8223
TR-TSV-000772,
TR-TSV-000773,
TR-NWT-000253,
T1S1/92-185;
n8223
N-822
CN8223EPF
AD6116
78P7200
BT8222EPFE
PROCESS CONTROL TIMER using 555 ic
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BT8222KPF
Abstract: atm header error checking 78P7200 CN8223 CN8223EPF e3 frame formatter
Text: CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
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CN8223
CN8223
TR-TSV-000772,
TR-TSV-000773,
TR-NWT-000253,
T1S1/92-185;
BT8222KPF
atm header error checking
78P7200
CN8223EPF
e3 frame formatter
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bip 109
Abstract: 78P7200 CN8223 CN8223EPF
Text: CN8223 ATM Transmitter/Receiver with UTOPIA Interface The CN8223 ATM Transmitter/Receiver with UTOPIA Level 1 interface provides a single-access ATM service termination for User-to-Network UNI and Network-to-Network Interfacing (NNI) in conformance with ATM Forum UNI and NNI
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CN8223
CN8223
TR-TSV-000772,
TR-TSV-000773,
TR-NWT-000253,
T1S1/92-185;
bip 109
78P7200
CN8223EPF
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RFC-1619
Abstract: foundation field bus protocol PLX9080 RFC1619 counter schematic diagram vhdl code CRC 32 vhdl code for scrambler descrambler VHDL CODE FOR HDLC controller
Text: PPP8 HDLC Core CC318f November 23, 1998 C ooreEl MicroSystems CoreEl MicroSystems 46750 Fremont Blvd. #208 Fremont, CA 94538 USA Phone: +1 510-770-2277 Fax: +1 510-770-2288 URL: www.coreel.com E-mail: [email protected] Features • • • • • • •
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CC318f)
RFC1619
16/32-bit
RFC-1619
foundation field bus protocol
PLX9080
counter schematic diagram
vhdl code CRC 32
vhdl code for scrambler descrambler
VHDL CODE FOR HDLC controller
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RFC1662
Abstract: crc verilog code 16 bit fifo generator xilinx datasheet spartan 4046 application circuits PLX9080 RFC1619
Text: PPP8 HDLC Core CC318f February 14, 2000 Product Specification AllianceCORE C ooreEl Facts Core Specifics See Table 1 Provided with Core Documentation Product Brief Datasheet Design Document Test Bench Design Document Test Scripts Design file formats
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CC318f)
RFC1619
RFC1662
RFC1662
crc verilog code 16 bit
fifo generator xilinx datasheet spartan
4046 application circuits
PLX9080
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8 bit microprocessor using vhdl
Abstract: vhdl code scrambler VHDL CODE FOR HDLC controller PLX9080 RFC1619 RFC1662
Text: PPP8 HDLC Core CC318f February 14, 2000 Product Specification AllianceCORE Facts C ooreEl Core Specifics See Table 1 Provided with Core Documentation Product Brief Datasheet Design Document Test Bench Design Document Test Scripts Design file formats VHDL Compiled, EDIF netlist
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CC318f)
RFC1619
RFC1662
8 bit microprocessor using vhdl
vhdl code scrambler
VHDL CODE FOR HDLC controller
PLX9080
RFC1662
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CTS Knights VCXO
Abstract: T7270 K95 (2 GATE) LB1276AF mtron Q11 DPDT S1 UM1 t7513b K95 Package 2754H2
Text: Data Sheet April 1998 T7264 U-Interface 2B1Q Transceiver Features • ■ U-interface 2B1Q transceiver — Range over 18 kft on 26 AWG — ISDN basic-rate 2B+D — Full-duplex, 2-wire operation — 2B1Q four-level line code — Conforms to ANSI North American Standard
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T7264
DS97-413ISDN
DS90-184SMOS,
AY93-032TCOM,
TN93-003TCOM)
CTS Knights VCXO
T7270
K95 (2 GATE)
LB1276AF
mtron
Q11 DPDT
S1 UM1
t7513b
K95 Package
2754H2
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Digital Alarm Clock using 8051
Abstract: chn 448 chn 706 CHN 632 CHN 703 RAM 2112 256 word 32.768mhz pin hole thru chn 608 microcontroller 8051 application of alarm clock octal tri state buffer ic
Text: áç XRT84L38 OCTAL T1/E1/J1 FRAMER FEBRUARY 2004 REV. 1.0.0 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications.
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XRT84L38
XRT84L38
Digital Alarm Clock using 8051
chn 448
chn 706
CHN 632
CHN 703
RAM 2112 256 word
32.768mhz pin hole thru
chn 608
microcontroller 8051 application of alarm clock
octal tri state buffer ic
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CHN G4 136
Abstract: chn7 SA8 357 TR54016 XRT83L38 XRT84L38 XRT84L38IB 7174B 8ch LOW SATURATION DRIVER C1-168
Text: XRT84L38 OCTAL T1/E1/J1 FRAMER SEPTEMBER 2006 REV. 1.0.1 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error
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XRT84L38
XRT84L38
CHN G4 136
chn7
SA8 357
TR54016
XRT83L38
XRT84L38IB
7174B
8ch LOW SATURATION DRIVER
C1-168
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CHN G4 124
Abstract: CHN G4 329
Text: áç XRT84L38 PRELIMINARY OCTAL T1/E1/J1 FRAMER JULY 2003 REV. P1.0.4 GENERAL DESCRIPTION The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications.
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XRT84L38
XRT84L38
CHN G4 124
CHN G4 329
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ssy 1920
Abstract: L8222
Text: llOii 1.0 Product Description - The Bt8222 ATM Physical Interface PHY) device is a receiver/transmitter which converts several types of frames to ATM cells and vice versa. The device contains framers for DS3, E3, E4, STS-1, STS-3c nd STM-1. This chapter provides an
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Bt8222
Bt8222,
Bt8222.
int103
L8222
Bt8222
ssy 1920
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S1 UM1
Abstract: B23-11 e.oc1 M3238 T7263
Text: Preliminary Data Sheet T7262/63 U-lnterface 2B1Q Transceiver FEATURES • U-lnterface 2B1Q T ransceiver - Range Over 18 kft on 26 AWG - ISDN Basic Rate 2B + D - Full Duplex, 2-Wire Operation - 2B1Q Four Level Line Code - Conforms to ANSI North American Standard T1.601 - 1988
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T7262/63
T7262
T7263
DS89-091SMC1S
S1 UM1
B23-11
e.oc1
M3238
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rsm 2814
Abstract: No abstract text available
Text: 1.0 Product Description - The Bt8209 and Bt8210 Switched Multimegabit Data Service SMDS Control and Reassembly Formatters (SCARF) provide a single-access SMDS service ter mination for connectionless data, “datagram,” transfer according to Bellcore TRTSV-000772 and TR-TSV-000773. Customer Premise Equipment (CPE) and
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Bt8209
Bt8210
TRTSV-000772
TR-TSV-000773.
TR-TSV-000774
TR-TSV-000775
0x2000-0x3FFF)
L8210
rsm 2814
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S1 UM1
Abstract: T-7270
Text: microelectronics Advance Data Sheet January 1997 group Lucent Technologies Bell Labs Innovations T7264 U-lnterface 2B1Q Transceiver ASIC Macrocell Features • U-interface 2B1Q transceiver — Range over 18 kft on 26 AWG — ISDN basic rate 2B+D — Full-duplex, two-wire operation
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T7264
S1 UM1
T-7270
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55185
Abstract: No abstract text available
Text: microelectronics Advance Data Sheet January 1997 group Lucent Technologies Bell Labs Innovations T7264 U-lnterface 2B1Q Transceiver ASIC Macrocell Features • U-interface 2B1Q transceiver — Range over 18 kft on 26 AWG — ISDN basic rate 2B+D — Full-duplex, two-wire operation
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T7264
-tRSLRSH5-5186
55185
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S1 UM1
Abstract: B1182 CTS Knights VCXO K95 (2 GATE) 2b1q encoding LB1276AF 2754H2 T7264 T7270 K95-K94
Text: m i c r o e l e c t r o n i c s Advance Data Sheet January 1997 g r o u p Lucent Technologies Bell Labs Innovations T7264 U-lnterface 2B1Q Transceiver ASIC Macrocell Features • U-interface 2B1Q transceiver — Range over 18 kft on 26 AWG — ISDN basic rate 2B+D
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T7264
S1 UM1
B1182
CTS Knights VCXO
K95 (2 GATE)
2b1q encoding
LB1276AF
2754H2
T7264
T7270
K95-K94
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L8222
Abstract: OQ 051
Text: 1.0 Product Description 1.1 Introduction Figure 1-1 is a detailed block diagram of the Bt8222. For transmission from the host system, octet-wide data is input from the UTOPIA or FIFO ports. The host data is assembled into ATM cells and then formatted for serial line transmission
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Bt8222.
L822201
L8222
OQ 051
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Untitled
Abstract: No abstract text available
Text: BROOKTREE CORP b3E B • 1^455^5 DDQ7G3T Interface Specification IS-210.15 SMDS C o n tro l and R e a sse m b ly F o r m a tte r Part # UGA-210 M arch, 1993 Brooktree Brooktree Corporation 9950 Barnes Canyon Road San Diego, CA 92121 USA 6 1 9 -4 5 2 -7 5 8 0
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IS-210
UGA-210
0007QM0
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CTS Knights VCXO
Abstract: SMSJ60C TAS220
Text: Data Sheet April 1998 microelectronics group Lucent Technologies Bell Labs Innovations T7264 U-lnterface 2B1Q Transceiver Features • U-interface 2B1Q transceiver — Range over 18 kft on 26 AWG — ISDN basic-rate 2B+D — Full-duplex, 2-wire operation — 2B1Q four-level line code
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T7264
44-pin
DS97-413ISDN
DS90-184SMOS,
AY93-032TCQM,
TN93-003TCQM)
CTS Knights VCXO
SMSJ60C
TAS220
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Untitled
Abstract: No abstract text available
Text: Data Sheet April 1998 microelectronics group Lucent Technologies Bell Labs Innovations T7264 U-lnterface 2B1Q Transceiver Features • U-interface 2B1Q transceiver — Range over 18 kft on 26 AWG — ISDN basic-rate 2B+D — Full-duplex, 2-wire operation — 2B1Q four-level line code
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T7264
T7264A)
T7264A
5002b
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