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    CPLD PINS TABLE Search Results

    CPLD PINS TABLE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    CS-DSDMDB09MF-010 Amphenol Cables on Demand Amphenol CS-DSDMDB09MF-010 9-Pin (DB9) Deluxe D-Sub Cable - Copper Shielded - Male / Female 10ft Datasheet
    CS-DSDMDB15MF-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB15MF-002.5 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Female 2.5ft Datasheet
    CS-DSDMDB15MM-025 Amphenol Cables on Demand Amphenol CS-DSDMDB15MM-025 15-Pin (DB15) Deluxe D-Sub Cable - Copper Shielded - Male / Male 25ft Datasheet
    CS-DSDMDB25MM-010 Amphenol Cables on Demand Amphenol CS-DSDMDB25MM-010 25-Pin (DB25) Deluxe D-Sub Cable - Copper Shielded - Male / Male 10ft Datasheet
    CS-DSDMDB37MM-002.5 Amphenol Cables on Demand Amphenol CS-DSDMDB37MM-002.5 37-Pin (DB37) Deluxe D-Sub Cable - Copper Shielded - Male / Male 2.5ft Datasheet

    CPLD PINS TABLE Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    WIDE BUS FAMILY

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 15K to 100K usable gates — 256 to 1536 macrocells — 92 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global control signal pins; 4 JTAG interface pins for


    Original     		Quantum38KTM WIDE BUS FAMILY PDF

    Untitled

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG


    Original     		Quantum38Kâ 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K PDF

    Untitled

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — 8 Dedicated Inputs including 4 clock pins and 4 global I/O control signal pins; 4 JTAG interface pins


    Original     		Quantum38KTM 38K15 144FBGA MIL-STD-883" /JESD22-A114-A 83MHz 66MHz" 125MHz 83MHz" Quantum38K PDF

    CY3LV010

    Abstract: 38K30 CYDH2200E 38K50
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs at ASIC Prices™ Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight Dedicated Inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan


    Original     		Quantum38KTM Quantum38K CY38K100 208-pin 208EQFP) CY3LV010 38K30 CYDH2200E 38K50 PDF

    208EQFP

    Abstract: No abstract text available
    Text: Quantum38K ISR™ CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and four global I/O control signal pins; four JTAG


    Original     		Quantum38KTM 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K 208EQFP PDF

    100K preset horizontal

    Abstract: LB 124 d LB 124 transistor verilog code for implementation of eeprom 38K30 j510
    Text: Quantum38K ISR™ CPLD Family PRELIMINARY CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight Dedicated Inputs including four clock pins and four global I/O control signal pins; four JTAG interface pins for reconfigurability/boundary scan


    Original     		Quantum38KTM CY38K100 208-pin 208EQFP) Quantum38K30 Quantum38K50 Quantum38K 100K preset horizontal LB 124 d LB 124 transistor verilog code for implementation of eeprom 38K30 j510 PDF

    a6252

    Abstract: CS144 TQ100 TQ144 XC9500XV XC95144XV
    Text: XC95144XV High-Performance CPLD R DS051 v2.2 August 27, 2001 1 Advance Product Specification Features Power Estimation • 144 macrocells with 3,200 usable gates • Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins)


    Original     		XC95144XV DS051 100-pin 144-pin XC9500XV a6252 CS144 TQ100 TQ144 PDF

    Untitled

    Abstract: No abstract text available
    Text: XC95144XV High-Performance CPLD DS051 v2.5 September 13, 2002 1 Features • • • • • • • • 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins)


    Original     		XC95144XV DS051 XC9500XV PDF

    XC95144

    Abstract: No abstract text available
    Text: XC95144XV High-Performance CPLD DS051 v2.8 April 15, 2005 1 Features • • • • • • • • 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins)


    Original     		XC95144XV DS051 XC9500XV 220oC. XC95144 PDF

    Untitled

    Abstract: No abstract text available
    Text: XC95144XV High-Performance CPLD DS051 v2.4 June 25, 2002 1 Features • • • • • • • • 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins)


    Original     		XC95144XV DS051 XC9500XV PDF

    Untitled

    Abstract: No abstract text available
    Text: XC95144XV High-Performance CPLD R DS051 v2.0 January 25, 2001 1 Advance Product Specification Features Power Estimation • 144 macrocells with 3,200 usable gates • Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins)


    Original     		XC95144XV DS051 100-pin 144-pin 54-input Indivi70 TQ100 TQ144 PDF

    Untitled

    Abstract: No abstract text available
    Text: XC95144XV High-Performance CPLD DS051 v2.6 June 18, 2003 1 Features • • • • • • • • 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins)


    Original     		XC95144XV DS051 100-pin 144-pin 54-input 220oC. PDF

    k3402

    Abstract: 131C-6 XC95144XV-7TQ144I CS144 TQ100 TQ144 XAPP361 XC9500XV XC95144XV
    Text: XC95144XV High-Performance CPLD DS051 v2.7 August 21, 2003 1 Features • • • • • • • • 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins)


    Original     		XC95144XV DS051 100-pin 144-pin 54-input 220oC. k3402 131C-6 XC95144XV-7TQ144I CS144 TQ100 TQ144 XAPP361 XC9500XV PDF

    38K30

    Abstract: DELTA39K CY3LV010
    Text: USE DELTA39K FOR Quantum38K™ ISR™ ALL NEW DESIGNS CPLD Family CPLDs Designed for Migration Features • High density — 30K to 100K usable gates — 512 to 1536 macrocells — 136 to 302 maximum I/O pins — Eight dedicated inputs including four clock pins and


    Original     		DELTA39KTM Quantum38KTM 16-Kb 48-Kb 125-MHz 18-mm Quantum38K30 Quantum38K50 Quantum38K Delta39K 38K30 CY3LV010 PDF

    XC95144

    Abstract: XC95144-10PQ100I PQ100 PQ160 TQ100 XC9500 XC95144-10PQ160I XC95144-15TQ100C
    Text: XC95144 In-System Programmable CPLD R DS067 v5.3 February 16, 2004 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins


    Original     		XC95144 DS067 36V18 PQ160 XC95144-10PQ100I PQ100 TQ100 XC9500 XC95144-10PQ160I XC95144-15TQ100C PDF

    TQ144

    Abstract: XAPP361 XC9500XV XC95288XV XC95288XV-10 XC95288XV-7
    Text: u XC95288XV High-Performance CPLD R DS050 v2.5 August 21, 2003 5 Features • • • • • • • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CSP (192 user I/O pins)


    Original     		XC95288XV DS050 144-pin 208-pin 280-pin 256-pin 54-input 220oC. TQ144 XAPP361 XC9500XV XC95288XV-10 XC95288XV-7 PDF

    Untitled

    Abstract: No abstract text available
    Text: u XC95288XV High-Performance CPLD R DS050 v2.6 April 15, 2005 5 Features • • • • • • • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CSP (192 user I/O pins)


    Original     		XC95288XV DS050 XC9500XV 220oC. PDF

    Untitled

    Abstract: No abstract text available
    Text: XC9536XV High-performance CPLD R DS053 v2.6 April 15, 2005 1 Features • • • • • • • • • 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins)


    Original     		XC9536XV DS053 XC9500XV 220oC. PDF

    DSA0092

    Abstract: No abstract text available
    Text: u XC95288XV High-Performance CPLD R DS050 v2.3 June 24, 2002 5 Features • • • • • • • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CSP (192 user I/O pins)


    Original     		XC95288XV DS050 XC9500XV DSA0092 PDF

    XC95108

    Abstract: XC95108-10PQ160C XC9510815PQ10 XC95108-7TQ100C
    Text: XC95108 In-System Programmable CPLD R DS066 v4.3 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates Up to 108 user I/O pins 5V in-system programmable


    Original     		XC95108 DS066 36V18 XC9500 PQ160 XC95108-10PQ160C XC9510815PQ10 XC95108-7TQ100C PDF

    xc9536

    Abstract: xc9536-7vq44 95xxx XC9536-7VQ44I xc9536-15vq44i XC9536-15VQ44C
    Text: XC9536 In-System Programmable CPLD R DS064 v6.2 April 15, 2005 5 Product Specification Features Description • • 5 ns pin-to-pin logic delays on all pins fCNT to 100 MHz • • • 36 macrocells with 800 usable gates Up to 34 user I/O pins 5V in-system programmable


    Original     		XC9536 DS064 36V18 xc9536-7vq44 95xxx XC9536-7VQ44I xc9536-15vq44i XC9536-15VQ44C PDF

    XC95144-15TQ100C

    Abstract: No abstract text available
    Text: XC95144 In-System Programmable CPLD R DS067 v5.4 April 15, 2005 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz • • • 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable


    Original     		XC95144 DS067 36V18 PQ160 XC95144-15TQ100C PDF

    XC95108-15TQ100C

    Abstract: XC95108-15PCG84C XC95108 XC95108-20TQ100I XC95108-15TQG100C XC95108-10PQG160I PQ100 PQG160 xc95108 tq100 XC95108-15TQ100I
    Text: XC95108 In-System Programmable CPLD R DS066 v4.4 April 3, 2006 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates Up to 108 user I/O pins 5V in-system programmable


    Original     		XC95108 DS066 36V18 XC9500 PQ160 XC95108-15TQ100C XC95108-15PCG84C XC95108-20TQ100I XC95108-15TQG100C XC95108-10PQG160I PQ100 PQG160 xc95108 tq100 XC95108-15TQ100I PDF

    XC95108-20TQ100I

    Abstract: XC95108 xc95108 tq100 XC95108-15PC84C XC95108-15TQ100I PC84 XC9500 7PQ100I xc95108-7 XC95108-7PQ100C
    Text: XC95108 In-System Programmable CPLD R DS066 v4.1 August 21, 2003 5 Product Specification Features Description • • 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz • • • 108 macrocells with 2,400 usable gates Up to 108 user I/O pins 5V in-system programmable


    Original     		XC95108 DS066 36V18 XC95108-20TQ100I xc95108 tq100 XC95108-15PC84C XC95108-15TQ100I PC84 XC9500 7PQ100I xc95108-7 XC95108-7PQ100C PDF