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    CY373 Search Results

    CY373 Datasheets (500)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY3732VP100-100AXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-100BAXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-100BBXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-100BGXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-100JXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-100NTXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-100NXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-100UXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-100YXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-125AXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-125BAXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-125BBXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-125BGXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-125JXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-125NTXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-125NXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-125UXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-125YXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-143AXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    CY3732VP100-143BAXC Cypress Semiconductor 5V, 3.3V, ISRTM High-Performance CPLDs Original PDF
    ...

    CY373 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    CY37384

    Abstract: CY37384V
    Text: PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes


    Original     		PDF CY37384 384-Macrocell CY37384 CY37384V

    CY37384

    Abstract: CY37384V cpld internal
    Text: Back PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Features — tPD = 15 ns — tS = 8 ns • 384 macrocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • •


    Original     		PDF CY37384V 384-Macrocell CY37384 CY37384V cpld internal

    ultraISR CABLE

    Abstract: No abstract text available
    Text: PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout. This makes Ultra37000 optimal for implementing on-board design changes using ISR without changing pinouts.


    Original     		PDF CY37384V 384-Macrocell ultraISR CABLE

    CY37512VP208-UMB

    Abstract: diagram PRESSURE cooker tsmc mos 45 CY37512 CY37384
    Text: Cypress Semiconductor Product Qualification Report QTP# 000605 VERSION 1.0 September, 2000 High-Performance CPLDs Family CY37384P208/ CY37384VP208 UltraLogic 384-Macrocell ISR™ CPLDs CY37512P208/ CY37512VP208 UltraLogic™ 512-Macrocell ISR™ CPLDs CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:


    Original     		PDF CY37384P208/ CY37384VP208 384-Macrocell CY37512P208/ CY37512VP208 512-Macrocell CY37384 /CY37512* CY37256P160-AC CY37512VP208-UMB diagram PRESSURE cooker tsmc mos 45 CY37512

    TMS3616

    Abstract: CY37384
    Text: PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes


    Original     		PDF CY37384 384-Macrocell 208-Lead 256-Lead TMS3616 CY37384

    cy37128 bsdl file

    Abstract: CYP37256 bsdl cy37512 AN1024 0X00 CY37032 CY37064 CY37128 CY37192 CY37
    Text: Using IEEE 1149.1 Boundary Scan JTAG With Cypress Ultra37000 CPLDs AN1024 Associated Project: No Associated Part Family: CY37512, CY37384, CY37256, CY37192, CY37128, CY37064, CY37032 GET FREE SAMPLES HERE Associated Application Notes: None Application Note Abstract


    Original     		PDF Ultra37000TM AN1024 CY37512, CY37384, CY37256, CY37192, CY37128, CY37064, CY37032 cy37128 bsdl file CYP37256 bsdl cy37512 AN1024 0X00 CY37032 CY37064 CY37128 CY37192 CY37

    CY37384

    Abstract: CY37384V
    Text: PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Features — tPD = 15 ns — tS = 8 ns • 384 macrocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • •


    Original     		PDF CY37384V 384-Macrocell CY37384 CY37384V

    CY37384

    Abstract: CY37384V
    Text: Back PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes


    Original     		PDF CY37384 384-Macrocell CY37384 CY37384V

    CY37512

    Abstract: CY37512V
    Text: Back PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes


    Original     		PDF CY37512V 512-Macrocell CY37512 CY37512V

    Device-List

    Abstract: cf745 04 p 24LC211 lattice im4a3-32 CF775 MICROCHIP 29F008 im4a3-64 ks24c01 ep320ipc ALL-11P2
    Text: Device List Adapter List Converter List for ALL-11 JUL. 2000 Introduction T he Device List lets you know exactly which devices the Universal Programmer currently supports. The Device List also lets you know which devices are supported directly by the standard DIP socket and which


    Original     		PDF ALL-11 Z86E73 Z86E83 Z89371 ADP-Z89371/-PL Z8E000 ADP-Z8E001 Z8E001 Device-List cf745 04 p 24LC211 lattice im4a3-32 CF775 MICROCHIP 29F008 im4a3-64 ks24c01 ep320ipc ALL-11P2

    CY37512P208-100UMB

    Abstract: CY37512P208-100UM CY37032VP44-100AI CY37256P160-83UM CY37064P44-154YMB CY37256P160-125UMB CERAMIC leaded CHIP CARRIER CLCC 68
    Text: Family PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes


    Original     		PDF Ultra37000TM 222-MHz CY37512P208-100UMB CY37512P208-100UM CY37032VP44-100AI CY37256P160-83UM CY37064P44-154YMB CY37256P160-125UMB CERAMIC leaded CHIP CARRIER CLCC 68

    Untitled

    Abstract: No abstract text available
    Text: CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — tS = 7.0 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • •


    Original     		PDF CY37256V 256-Macrocell

    CY37032VP44-100AI

    Abstract: CY37064P44-154YMB CY37512P208-100UMB
    Text: Family Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs Features General Description • In-System Reprogrammable™ ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes


    Original     		PDF Ultra37000TM CY37032VP44-100AI CY37064P44-154YMB CY37512P208-100UMB

    CY37384

    Abstract: CY37384V L0651
    Text: = j— PRELIMINARY T. # CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout.


    OCR Scan     		PDF CY37384V 384-Macrocell CY37384 CY37384V L0651

    CY37384

    Abstract: tms 0119 256-pin Plastic BGA 17 x 17
    Text: = m m m !Æ '^ r ^ r : c Q P R £ U M lm fíY CY37384 i í.-.-.-.í k v / k., UltraLogic 384-Macrocell ISR™ CPLD Features — ts = 5.5 ns — tc o = 6 ns • 384 m a cro c ells in 24 logic blo cks • P ro d uct-term clocking • In-S ystem R ep ro g ra m m ab le ™ IS R ™


    OCR Scan     		PDF CY37384 384-Macrocell 208-pin 256-lead CY37384 tms 0119 256-pin Plastic BGA 17 x 17

    CY37384

    Abstract: CY37384V
    Text: = m m m !Æ '^ r ^ r : c Q i r o P R £ u m A fíY CY37384 o — UltraLogic 384-Macrocell ISR™ CPLD Features — ts = 5.5 ns — tco = 6.0 ns • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ • • • • • • • •


    OCR Scan     		PDF CY37384 384-Macrocell 208-pin 256-lead CY37384 CY37384V

    y373

    Abstract: CY37384
    Text: ^ ^ ^ PRELIMINARY CYPRKSS CY37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — t co = 6.0 ns • 384 m a cro c ells in 24 logic blocks • P ro d uct-term clo ckin g • In-S ystem R e p ro g ra m m ab le ™ IS R ™ • IE E E 1149.1 JTAG b o u n d a ry scan


    OCR Scan     		PDF CY37384 384-Macrocell y373 CY37384

    L256L

    Abstract: No abstract text available
    Text: ^ ^ ^ PRELIMINARY CYPRKSS CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully R o u tab le w ith 10 0% L og ic U tilization Features — JT A G -co m p liant o n -b o a rd p ro g ram m in g T he C Y 3 73 84V is desig ned w ith a robust routing arch itecture


    OCR Scan     		PDF CY37384V 384-Macrocell L256L

    Untitled

    Abstract: No abstract text available
    Text: Xgjf PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD — tPD = 15 ns Features — ts = 8 ns • 384 macrocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 8 ns Product-term clocking IEEE 1149.1 JTAG boundary scan


    OCR Scan     		PDF CY37384V 384-Macrocell 208-pin 256-lead

    O10S

    Abstract: No abstract text available
    Text: PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD — t PD = 15 ns Features — ts = 8 ns • 384 macnocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — — JTAG-compliant on-board programming — Design changes d on’t cause pinout changes


    OCR Scan     		PDF CY37384V 384-Macrocell O10S

    Untitled

    Abstract: No abstract text available
    Text: ^ jjjjjy .•/$ $$$$I ♦ PRELIMINARY < ij /t t5;*^ ' CY37512 UltraLogic 512-Macrocell ISR™ CPLD — tco = 6 ns Features • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ (ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes


    OCR Scan     		PDF CY37512 512-Macrocell

    Untitled

    Abstract: No abstract text available
    Text: Xgjf PRELIMINARY CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming


    OCR Scan     		PDF CY37256V 256-Macrocell 160-pin 208-pin 256-lead CY37256, CY37128/37128V, Y37192/37192V, CY37384/37384V, CY37512/37512V

    clcc land pattern

    Abstract: CY37512VP208-66UMB CY37032VP44-100AI CY37064P44-154YMB CY37256P160-125UMB TO-220AB/clcc land pattern
    Text: CYPRESS PRELIMINARY Ultra37000 CPLD Family 5V, 3.3V, ISR™ High-Performance CPLDs General Description Features • In-System Reprogram mable ISR™ CMOS CPLDs — JTAG interface for reconfigurability — Design changes don’t cause pinout changes — Design changes don’t cause timing changes


    OCR Scan     		PDF Ultra37000TM Ultra37000 22V10 clcc land pattern CY37512VP208-66UMB CY37032VP44-100AI CY37064P44-154YMB CY37256P160-125UMB TO-220AB/clcc land pattern

    37-25615

    Abstract: CY37256 CY37256P160-125UMB
    Text: UltraLogic 256-Macrocell ISR™ CPLD Features — tCo = 4 -5 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 256 macrocells in sixteen logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os


    OCR Scan     		PDF 256-Macrocell 160-pin 208-pin 256-lead CY372n 37-25615 CY37256 CY37256P160-125UMB