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    CY7C1313BV18 Search Results

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    CY7C1313BV18 Price and Stock

    Rochester Electronics LLC CY7C1313BV18-167BZC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1313BV18-167BZC Tray 10
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    Infineon Technologies AG CY7C1313BV18-167BZC

    IC SRAM 18MBIT PAR 165FBGA
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    DigiKey CY7C1313BV18-167BZC Tray 136
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    Rochester Electronics LLC CY7C1313BV18-200BZC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1313BV18-200BZC Tray 9
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    Infineon Technologies AG CY7C1313BV18-200BZC

    IC SRAM 18MBIT PARALLEL 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1313BV18-200BZC Tray 136
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    Infineon Technologies AG CY7C1313BV18-250BZC

    IC SRAM 18MBIT PAR 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1313BV18-250BZC Tray 136
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    CY7C1313BV18 Datasheets (9)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1313BV18 Cypress Semiconductor 18-Mbit QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1313BV18-167BZC Cypress Semiconductor 18-Mbit QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1313BV18-167BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 167MHZ 165FBGA Original PDF
    CY7C1313BV18-167BZCT Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 167MHZ 165FBGA Original PDF
    CY7C1313BV18-167BZXC Cypress Semiconductor 18-Mbit QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1313BV18-200BZC Cypress Semiconductor 18-Mbit QDR -II SRAM 4-Word Burst Architecture Original PDF
    CY7C1313BV18-200BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 200MHZ 165FBGA Original PDF
    CY7C1313BV18-250BZC Cypress Semiconductor 18-Mbit QDR -II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V Original PDF
    CY7C1313BV18-250BZC Cypress Semiconductor Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 250MHZ 165FBGA Original PDF

    CY7C1313BV18 Datasheets Context Search

    Catalog Datasheet MFG & Type Document Tags PDF

    CY7C1311BV18

    Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
    Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions


    Original
    CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit CY7C1911BV18, CY7C1315BV18 PDF

    CY7C1311BV18

    Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
    Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz 600MHz) SelecCY7C1911BV18 278-MHz PDF

    CY7C1311BV18

    Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
    Text: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth


    Original
    CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 PDF

    CY7C1911BV18

    Abstract: CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1313
    Text: CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz clock for high bandwidth


    Original
    CY7C1311BV18, CY7C1911BV18 CY7C1313BV18, CY7C1315BV18 18-Mbit CY7C1911BV18 CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1313 PDF

    Untitled

    Abstract: No abstract text available
    Text: CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300-MHz clock for high bandwidth


    Original
    CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 300-MHz 600MHz) CY7C1911BV18 BB165E BB165D PDF

    CY7C1311BV18

    Abstract: CY7C1313BV18 CY7C1315BV18 CY7C1911BV18
    Text: CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 PRELIMINARY 18-Mbit QDR -II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth


    Original
    CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit 250-MHz CY7C1311BV18 CY7C1313BV18 CY7C1315BV18 CY7C1911BV18 PDF

    CY7C1338-100AXC

    Abstract: gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC
    Text: CYPRESS / GALVANTECH # - Connect pin 14 FT pin to Vss CY7C1019BV33-15VC GS71108AJ-12 & - Does not support 1.8V I/O CY7C1019BV33-15VXC GS71108AGJ-12 * - Tie down extra four I/Os with resistor CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12


    Original
    CY7C1019BV33-15VC GS71108AJ-12 CY7C1019BV33-15VXC GS71108AGJ-12 CY7C1019BV33-15ZC GS71108ATP-12 CY7C1019BV33-15ZXC GS71108AGP-12 CY7C1019CV33-10VC GS71108AJ-10 CY7C1338-100AXC gvt7164d32q-6 CY7C1049BV33-12VXC CY7C1363C-133AC CY7C1021DV33-12ZXC CY7C1460AV25-200AXC CY7C1338G-100AC CY7C1041V33-12ZXC CY7C1460V33-200AXC CY7C1021DV33-10ZXC PDF

    CY7C1313AV18-250BZC

    Abstract: EP1S60 EP2S60F1020C5ES F1020 v32-88
    Text: Interfacing QDRII+ & QDRII with Stratix II, Stratix II GX, Stratix, & Stratix GX Devices Application Note 326 May 2008, ver. 5.1 Introduction Synchronous static RAM SRAM architectures support the high throughput requirements of communications, networking, and digital


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