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    CY7C1315JV18 Price and Stock

    Infineon Technologies AG CY7C1315JV18-300BZC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1315JV18-300BZC Tray
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    Rochester Electronics LLC CY7C1315JV18-300BZC

    IC SRAM 18MBIT PARALLEL 165FBGA
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    DigiKey CY7C1315JV18-300BZC Tray 9
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    • 10 $37.32
    • 100 $37.32
    • 1000 $37.32
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    Infineon Technologies AG CY7C1315JV18-300BZXC

    IC SRAM 18MBIT PARALLEL 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1315JV18-300BZXC Tray
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    Rochester Electronics LLC CY7C1315JV18-300BZXC

    IC SRAM 18MBIT PARALLEL 165FBGA
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1315JV18-300BZXC Tray 9
    • 1 -
    • 10 $37.32
    • 100 $37.32
    • 1000 $37.32
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    Cypress Semiconductor CY7C1315JV18-300BZC

    CY7C1315JV18-300BZC
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    Verical CY7C1315JV18-300BZC 3,459 9
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    Rochester Electronics CY7C1315JV18-300BZC 3,463 1
    • 1 $35.88
    • 10 $35.88
    • 100 $33.73
    • 1000 $30.5
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    CY7C1315JV18 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    CY7C1315JV18-300BZC Cypress Semiconductor 18-Mbit QDR(R) II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V Original PDF
    CY7C1315JV18-300BZXC Cypress Semiconductor 18-Mbit QDR(R) II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 1.7 to 1.9 V Original PDF

    CY7C1315JV18 Datasheets Context Search

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    Untitled

    Abstract: No abstract text available
    Text: CY7C1311JV18, CY7C1911JV18 CY7C1313JV18, CY7C1315JV18 18-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1311JV18 – 2M x 8 ■ 300 MHz Clock for High Bandwidth


    Original
    PDF 18-Mbit CY7C1311JV18, CY7C1911JV18 CY7C1313JV18, CY7C1315JV18 CY7C1311JV18 CY7C1911JV18 CY7C1313JV18

    Untitled

    Abstract: No abstract text available
    Text: CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 18-Mbit QDR II SRAM 4-Word Burst Architecture Features Configurations • Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1311JV18 – 2M x 8 ■ 300 MHz Clock for High Bandwidth


    Original
    PDF CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 18-Mbit CY7C1311JV18 CY7C1313JV18 CY7C1315JV18