CY7C1320V18 Search Results

CY7C1320V18 Datasheets (5)

Part	ECAD Model	Manufacturer	Description	Curated	Datasheet Type	PDF
CY7C1320V18		Cypress Semiconductor	18-Mb DDR-II SRAM Two-word Burst Architecture		Original	PDF
CY7C1320V18-167BZC		Cypress Semiconductor	18-Mb DDR-II SRAM two-word burst architecture, 167MHz		Original	PDF
CY7C1320V18-200BZC		Cypress Semiconductor	18-Mb DDR-II SRAM two-word burst architecture, 200MHz		Original	PDF
CY7C1320V18-250BZC		Cypress Semiconductor	18-Mb DDR-II SRAM two-word burst architecture, 250MHz		Original	PDF
CY7C1320V18-300BZC		Cypress Semiconductor	18-Mb DDR-II SRAM two-word burst architecture, 300MHz		Original	PDF

CY7C1320V18 Datasheets Context Search

Catalog Datasheet	MFG & Type	Document Tags	PDF
CY7C1316V18 Abstract: CY7C1318V18 CY7C1320V18 Text: CY7C1316V18 CY7C1318V18 CY7C1320V18 PRELIMINARY 18-Mb DDR-II SRAM Two-word Burst Architecture Features Functional Description • 18-Mb density 2M x 8, 1M x 18, 512K x 36 — Supports concurrent transactions • 250-MHz clock for high vandwidth • Two-word burst for reducing address bus frequency	Original	CY7C1316V18 CY7C1318V18 CY7C1320V18 18-Mb 250-MHz CY7C1316V18/CY7C1318V18/CY7C1320V18 CY7C1316V18 CY7C1318V18 CY7C1320V18	PDF
Untitled Abstract: No abstract text available Text: CY7C1316V18 CY7C1318V18 CY7C1320V18 PRELIMINARY 18-Mb DDR -II SRAM 2-Word Burst Architecture Features Functional Description • 18-Mb density 2M x 8, 1M x 18, 512K x 36 • 250-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1316V18 CY7C1318V18 CY7C1320V18 18-Mb 250-MHz 13x15 pit18/CY7C1320V18 300-MHz	PDF
CY7C1316V18 Abstract: CY7C1318V18 CY7C1320V18 Text: 316V18 CY7C1316V18 CY7C1318V18 CY7C1320V18 ADVANCE INFORMATION 18-Mb 2-Word Burst SRAM with DDR-II Architecture Features Functional Description • 18-Mb Density 2M x 8, 1M x 18, 512K x 36 — Supports concurrent transactions • 300-MHz Clock for High Bandwidth	Original	316V18 CY7C1316V18 CY7C1318V18 CY7C1320V18 18-Mb 300-MHz CY7C1316V18 CY7C1318V18 CY7C1320V18	PDF
CY7C1322V25 Abstract: CY7C1397V25 Text: 397V25 CY7C1397V25 CY7C1322V25 ADVANCE INFORMATION 18-Mb 2-Word Burst SRAM with DDR-I Architecture Features Functional Description • 18-Mb Density 1M x 18, 512K x 36 — Supports concurrent transactions • 300-MHz Clock for High Bandwidth • 2-Word Burst for reducing address bus frequency	Original	397V25 CY7C1397V25 CY7C1322V25 18-Mb 300-MHz CY7C1397V25/CY7C1322V25 CY7C1322V25 CY7C1397V25	PDF