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CY7C1614KV18 Abstract: CY7C1612KV18-300BZXI CY7C1614KV18-250BZXC CY7C1612KV18 Text: CY7C1610KV18, CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 ADVANCE INFORMATION 144-Mbit QDR -II SRAM 2-Word Burst Architecture Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth	Original	PDF	CY7C1610KV18, CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 144-Mbit CY7C1610KV18 CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 CY7C1612KV18-300BZXI CY7C1614KV18-250BZXC CY7C1612KV18
CY7C1614KV18 Abstract: CY7C1612KV18-300BZXI Text: CY7C1610KV18, CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 144-Mbit QDR II SRAM 2-Word Burst Architecture 144-Mbit QDR ® II SRAM 2-Word Burst Architecture Features Configuration Separate independent read and write data ports ❐ Supports concurrent transactions	Original	PDF	144-Mbit CY7C1610KV18, CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 CY7C1610KV18 CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 CY7C1612KV18-300BZXI
Untitled Abstract: No abstract text available Text: CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 144-Mbit QDR II SRAM 2-Word Burst Architecture 144-Mbit QDR ® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1625KV18 – 16 M x 9	Original	PDF	144-Mbit CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 CY7C1625KV18 CY7C1612KV18 333-MHz
Untitled Abstract: No abstract text available Text: CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR II SRAM Two-Word Burst Architecture 144-Mbit QDR ® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1625KV18 – 16 M x 9	Original	PDF	CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit 360-MHz
Untitled Abstract: No abstract text available Text: CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR II SRAM Two-Word Burst Architecture 144-Mbit QDR ® II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1625KV18 – 16 M x 9	Original	PDF	CY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit CY7C1625KV18 CY7C1612KV18 333-MHz
CY7C1612KV18 Abstract: No abstract text available Text: CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 144-Mbit QDR II SRAM 2-Word Burst Architecture 144-Mbit QDR ® II SRAM 2-Word Burst Architecture Features Configurations Separate independent read and write data ports ❐ Supports concurrent transactions CY7C1625KV18 – 16 M x 9	Original	PDF	144-Mbit CY7C1625KV18 CY7C1612KV18, CY7C1614KV18 CY7C1625KV18 CY7C1612KV18 333-MHz CY7C1612KV18