DDR1 SDRAM Search Results

DDR1 SDRAM Result Highlights (5)

Part	Manufacturer	Description
TPS51116MPWPEP	Texas Instruments	Enhanced Product DDR1, DDR2, DDR3 Switcher and LDO 20-HTSSOP -55 to 125
V62/12602-01XE	Texas Instruments	Enhanced Product DDR1, DDR2, DDR3 Switcher and LDO 20-HTSSOP -55 to 125
TPS51116MPWPREP	Texas Instruments	Enhanced Product DDR1, DDR2, DDR3 Switcher and LDO 20-HTSSOP -55 to 125
V62/12602-01XE-T	Texas Instruments	Enhanced Product DDR1, DDR2, DDR3 Switcher and LDO 20-HTSSOP -55 to 125
AM1705DPTPD4	Texas Instruments	Sitara Processor: ARM9, SDRAM, Ethernet 176-HLQFP -40 to 90

DDR1 SDRAM Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
ddr ram repair Abstract: JESD79E JESD209 JESD209A DDR1 Ram Jedec JESD209 E2678A DDR 2 RAM REPAIR DSA91304A N5426A Text: Agilent U7233A DDR1 Compliance Test Application with LPDDR and mobile-DDR Support for Infiniium Series Oscilloscopes Data Sheet Test, debug and characterize your DDR1 designs quickly and easily The Agilent Technologies U7233A DDR1 compliance test application	Original	U7233A U7233A JESD79E JESD209A application1571 5989-7366EN ddr ram repair JESD209 DDR1 Ram Jedec JESD209 E2678A DDR 2 RAM REPAIR DSA91304A N5426A	PDF
Untitled Abstract: No abstract text available Text: Data Sheet Rev. 1.0 SDU12872H1BF2MT-50R 07-Apr-08 184-pin DDR1 PC3200 ECC DDR-SDRAM Module 01.2 5 13 4.7 DIMM 1GB DDR400 in TSOP Technique Features: • • • 184-pin 72-bit DDR1 Dual In-line Memory Module for desktop applications. DDR1-400 3.0-3-3 (CL-tRCD-tRP), 64Mx8 organized	Original	SDU12872H1BF2MT-50R 07-Apr-08 184-pin PC3200 DDR400 72-bit DDR1-400 64Mx8 400Mbps	PDF
ddr3 MTBF Abstract: No abstract text available Text: VCN60/70 Series www.murata-ps.com High Efﬁciency, High Current Density, 60 or 70 Amp Single Inline Package DC/DC Converters DESCRIPTION ESCRIPTIO ON NOT RECOMMENDED FOR NEW DESIGNS Designed signed to su support upport DDR1 DDR1, 1, DDR2 and DDR3 SDRA SDRAM	Original	VCN60/70 N60/70 ddr3 MTBF	PDF
ddr3 MTBF Abstract: SENSE23 4sp560m t Text: VCN60/70 Series www.murata-ps.com High Efﬁciency, High Current Density, 60 or 70 Amp Single Inline Package DC/DC Converters DESCRIPTION ESCRIPTIO ON Designed signed to su support upport DDR1 DDR1, 1, DDR2 and DDR3 SDRA SDRAM AM memoryy power requ requirements,	Original	VCN60/70 N60/70 ddr3 MTBF SENSE23 4sp560m t	PDF
modelsim 6.3f Abstract: LFXP2-5E-5TN144C LFE3-17EA LFE3-17EA6FN484C LFE3-17E-6FN484CES sdram verilog lfxp25e5tn144c lfe3-17ea-6fn484c BT 1490 ddr2 pinouts Text: DDR1 & DDR2 SDRAM Controller IP Cores User’s Guide August 2010 ipug35_04.7 Table of Contents Chapter 1. Introduction . 5 Quick Facts . 5	Original	ipug35 LFSC3GA25E-6F900C modelsim 6.3f LFXP2-5E-5TN144C LFE3-17EA LFE3-17EA6FN484C LFE3-17E-6FN484CES sdram verilog lfxp25e5tn144c lfe3-17ea-6fn484c BT 1490 ddr2 pinouts	PDF
micron ddr3 Abstract: DDR3 timing diagram DDR3 model verilog codes Verilog DDR3 memory model micron memory model for ddr3 MT41J128M8 Verilog DDR memory model DDR3 "application note" DDR3 DQ flip flop IC Text: Maxim > Design Support > App Notes > T/E Carrier and Packetized > APP 5120 Keywords: DDR1, DDR3, jitter, buffer, TDMoP, TDM over packet, DDR, SDRAM, PDV, PSN, double data rate APPLICATION NOTE 5120 Aug 26, 2011 Using a DDR3 Memory Module with the DS34S132	Original	DS34S132 DS34S132, 32-point DS34S132 256ms 32-port com/an5120 micron ddr3 DDR3 timing diagram DDR3 model verilog codes Verilog DDR3 memory model micron memory model for ddr3 MT41J128M8 Verilog DDR memory model DDR3 "application note" DDR3 DQ flip flop IC	PDF
Untitled Abstract: No abstract text available Text: Datasheet Regulator IC Series for Automotive Termination Regulator for DDR-SDRAMs BD35395FJ-M General Description Key Specifications         BD35395FJ-M is a termination regulator compatible with JEDEC DDR1/2/3/3L-SDRAM, which functions as a linear	Original	BD35395FJ-M BD35395FJ-M	PDF
Untitled Abstract: No abstract text available Text: Datasheet 1.0V to 5.5V, 1A 1ch Termination Regulators for DDR-SDRAMs BD3539FVM BD3539NUX General Description Key Specifications          BD3539 is a termination regulator that complies with JEDEC requirements for DDR1-SDRAM, DDR2-SDRAM, and DDR3-SDRAM. This linear power	Original	BD3539FVM BD3539NUX BD3539	PDF
Untitled Abstract: No abstract text available Text: VCN60/70 Series High Efficiency, High Current Density, 60 or 70 Amp Single Inline Package DC/DC Converters DESCRIPTION Designed to support DDR1, DDR2 and DDR3 SDRAM memory power requirements, the VCN60/70 Series point-of-load, non-isolated DC/DC converters have the high performance	Original	VCN60/70	PDF
Untitled Abstract: No abstract text available Text: Datasheet 1.0V to 5.5V, 1A 1ch Termination Regulator for DDR-SDRAMs BD35390FJ Key Specifications General Description          BD35390FJ is a termination regulator that complies with JEDEC requirements for DDR1/2/3-SDRAM. This linear	Original	BD35390FJ BD35390FJ	PDF
mpc8543 Abstract: POWERPC E500 instruction set MPC8548 MPC8548E MPC8545 Text: Integrated Communications Processors MPC8548E PowerQUICC III Processor MPC8548/E PRODUCT SOLUTION Key Features The MPC8548E networking/telecom processor e500 core includes 512 KB L2 cache, an integrated XOR Acceleration security engine, 64-bit DDR1/2 scaling to 667	Original	MPC8548E MPC8548/E MPC8548E 64-bit 32-bit 783-pin MPC8548PQIIIFS mpc8543 POWERPC E500 instruction set MPC8548 MPC8545	PDF
4SP560M T Abstract: iso 9001 sanyo United Chemi-Con Text: VCN60/70 Series High Efﬁciency, High Current Density, 60 or 70 Amp Single Inline Package DC/DC Converters DESCRIPTION Designed to support DDR1, DDR2 and DDR3 SDRAM memory power requirements, the VCN60/70 Series point-of-load, non-isolated DC/DC converters have the high performance	Original	VCN60/70 4SP560M T iso 9001 sanyo United Chemi-Con	PDF
jedec MS-012-AA Abstract: SP2996BEN CES7002A SP2996B Text: Advanced SP2996B 2A Bus Termination Regulator VIN 1 FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection	Original	SP2996B 25VTT) SP2996B SP2996BEN/TR SP2996BEN-L-/TR 935-7600m jedec MS-012-AA SP2996BEN CES7002A	PDF
Untitled Abstract: No abstract text available Text: UNISONIC TECHNOLOGIES CO., LTD UR5517 LINEAR INTEGRATED CIRCUIT 3A DDR BUS TERMINATION REGULATOR DESCRIPTION The UR5517 is a linear regulator which provides up to 3 Amp bi-directional sourcing and sinking capability for DDR1/2/3 SDRAM bus terminator applications. It only requires 20uF of ceramic output	Original	UR5517 UR5517 QW-R102-041	PDF

UR5517 Abstract: MSOP-10 s3h-i Text: UNISONIC TECHNOLOGIES CO., LTD UR5517 Preliminary LINEAR INTEGRATED CIRCUIT 3A DDR BUS TERMINATION REGULATOR DESCRIPTION The UR5517 is a linear regulator which provides up to 3 Amp bi-directional sourcing and sinking capability for DDR1/2/3 SDRAM bus terminator applications. It only requires 20uF of ceramic output	Original	UR5517 UR5517 MSOP-10 QW-R102-041 MSOP-10 s3h-i	PDF
JESD8-15a Abstract: ITT RZ2 SP2996 SP2996B CES7002A SP2996BEN TRANSISTOR HANDLING 2A Text: SP2996B 2 Amp DDR Bus Termination Regulator FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection ■ Integrated Power MOSFETs	Original	SP2996B 25VTT) SP2996B 188uF JESD8-15a ITT RZ2 SP2996 CES7002A SP2996BEN TRANSISTOR HANDLING 2A	PDF
Untitled Abstract: No abstract text available Text: Preliminary SP2996B 2A Bus Termination Regulator VIN 1 FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection	Original	SP2996B 25VTT) SP2996B SP2996BEN/TR SP2996BEN-L-/TR 935-7600m	PDF
T37Z Abstract: DD128 TSOP 66 pin Package thermal resistance DD128M82U3BB6 267-Mbps Text: 1 GigaBit Stacked DDR1 SDRAM 128M x 8 DD55E, DD55ER Features • Low Profile 66 Ball Two-High Stacked Die micropede BGA • 77% Space Savings Over Two 66 Pin TSOP Packages • 50% Space Savings Over Two 60 Ball BGA Packages • Significant Space Savings and Reduced Parasitics and	Original	DD55E, DD55ER DD54ER) DDR400) DD128M82U3BA DD55E 3887x132 DD55E) T37Z DD128 TSOP 66 pin Package thermal resistance DD128M82U3BB6 267-Mbps	PDF
Untitled Abstract: No abstract text available Text: Data Sheet Rev.1.1 22.02.2010 512MB DDR1 – SDRAM SO-DIMM Features: Features: 1 200-pin 64-bit Small Outline, Dual-In-Line Double 200 PIN SO-DIMM SDN06464K1BE1HY-50R 1 512MB DDR PC3200 1 1 TSOP Technique RoHS compliant Options: 1 Frequency / Latency DDR 400 MHz CL3	Original	512MB 200-pin 64-bit SDN06464K1BE1HY-50R PC3200 D-12681	PDF
SP2996B Abstract: 470uF 25V TANT REGULATOR 2A SP2996BEN CES7002A Text: SP2996B 2 Amp DDR Bus Termination Regulator FEATURES • Capable of sourcing and sinking 2A Continuous current ■ Supports both DDR1 1.25VTT and DDR2 (0.9VTT) requirements ■ Low Output Voltage Offset, + 20mV ■ Thermal and Current Limit Protection ■ Integrated Power MOSFETs	Original	SP2996B 25VTT) SP2996B Aug16-05 SP2996BEN SP2996BEN/TR SP2996BEN-L/TR 470uF 25V TANT REGULATOR 2A SP2996BEN CES7002A	PDF
equivalent for transistor tt 2222 Abstract: BD3539 S 35390 bd35390fj MCR031002 Text: Hi-performance Regulator IC Series for PCs Termination Regulator for DDR-SDRAMs BD35390FJ No.09030EAT25 ●Description BD35390FJ is a termination regulator compatible with JEDEC DDR1/2/3-SDRAM, which functions as a linear power supply incorporating an N-channel MOSFET and provides a sink/source current capability up to 1A respectively. A built-in	Original	BD35390FJ 09030EAT25 BD35390FJ R0039A equivalent for transistor tt 2222 BD3539 S 35390 MCR031002	PDF
DD256M Abstract: T37Z TSOP 66 Package thermal resistance Text: 1 GigaBit Stacked DDR1 SDRAM DD54E, DD54ER 256M x 4 Features • Low Profile 66 Ball Two-High Stacked Die micropede BGA • 77% Space Savings Over Two 66 Pin TSOP Packages • 50% Space Savings Over Two 60 Ball BGA Packages • Significant Space Savings and Reduced Parasitics and	Original	DD54E, DD54ER DD54ER) DDR400) DD256M42U3BA DD54E 3887x132 DD54E) DD256M T37Z TSOP 66 Package thermal resistance	PDF
Untitled Abstract: No abstract text available Text: LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR1-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot	Original	LP2998 SSTL-18	PDF
Untitled Abstract: No abstract text available Text: LP2998 DDR-I and DDR-II Termination Regulator General Description Features The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR1-SDRAM and DDR-II memory. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot	Original	LP2998 SSTL-18	PDF

DDR1 SDRAM Search Results

DDR1 SDRAM Result Highlights (5)

DDR1 SDRAM Datasheets Context Search

ddr ram repair

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ddr3 MTBF

ddr3 MTBF

modelsim 6.3f

micron ddr3

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mpc8543

4SP560M T

jedec MS-012-AA

Untitled

UR5517

JESD8-15a

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T37Z

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SP2996B

equivalent for transistor tt 2222

DD256M

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