PC 1498H
Abstract: 1444H A6779 1484H PAR64 REQ64
Text: DMA Controller Unit 19 This chapter describes the integrated Direct Memory Access DMA Controller Unit. The operation modes, setup, external interface, and implementation of the DMA Controller are detailed in this chapter. 19.1 Overview The DMA Controller provides low-latency, high-throughput data transfer capability. The DMA
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PC 1498H
1444H
A6779
1484H
PAR64
REQ64
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Z16C3001ZCO
Abstract: Z8018600ZCO Z16C30 Z16C32 Z16C35 Z8018100ZCO ZEPMDC00001 68-PIN Zilog Z16C30
Text: Datacom Z80/S180 Embedded Controllers Block Diagram Zilog Superintegration Pr oducts Guide 32-Byte Tx F1F0 Tx DMA 32-Byte Rx F1F0 Rx DMA 32-Byte Tx F1F0 Tx 32-Byte Rx F1F0 Rx DMA BRG BIU SCC BRG DPLL DPLL DMA BRG Tx DMA 32-Byte Tx F1F0 Tx Rx DMA 32-Byte
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Z80/S180
32-Byte
Z16C35
Z16C30
Z16C32
Z16C3001ZCO
Z8018600ZCO
Z16C30
Z16C32
Z16C35
Z8018100ZCO
ZEPMDC00001
68-PIN
Zilog Z16C30
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AMBA AXI dma controller designer user guide
Abstract: DMA-330 awid communication protocol FD001 FD001 User Guide ARM DUI 0333 AMBA AXI designer user guide DMA Controller PL330 Technical Reference Manual PL330 PL330 equivalent JEP106
Text: AMBA DMA Controller DMA-330 Revision: r1p0 Technical Reference Manual Copyright 2007, 2009 ARM Limited. All rights reserved. ARM DDI 0424B ID112209 AMBA DMA Controller DMA-330 Technical Reference Manual Copyright © 2007, 2009 ARM Limited. All rights reserved.
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DMA-330
0424B
ID112209)
32-bit
ID112209
AMBA AXI dma controller designer user guide
DMA-330
awid communication protocol
FD001
FD001 User Guide ARM DUI 0333
AMBA AXI designer user guide
DMA Controller PL330 Technical Reference Manual
PL330
PL330 equivalent
JEP106
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MC68322
Abstract: No abstract text available
Text: SECTION 8 DMA INTERFACE The MC68322 DMA interface provides support for high speed data transfers between external sources and DRAM. The DMA interface contains two channels: the parallel port DMA PDMA and the general purpose DMA (GDMA). Both DMA channels are single ended channels and operate independently from each
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MC68322
16-bit
EC000
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ML67Q5003A
Abstract: ML675001A ML67Q5002A Q5003 ML675001 ML67Q5002 ML67Q5003
Text: ML675001/Q5002/Q5003 Series DMA Functional Restrictions Introduction This document describes a limitation in usage of the DMA controller of Oki's ML675k series of MCUs. The proper use of the DMA resource is also described. Description DMA Functional Restriction when
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ML675001/Q5002/Q5003
ML675k
ML675001,
ML67Q5002,
ML67Q5003,
ML675001A,
ML67Q5002A,
ML67Q5003A
ML67Q5003A
ML675001A
ML67Q5002A
Q5003
ML675001
ML67Q5002
ML67Q5003
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DMA Controller DMA-330 Supplement to AMBA Designer ADR-301 User Guide
Abstract: adr-301 DMA-330 AMBA AXI dma controller designer user guide armv7-a dma 330 user guide pl330 DMA Controller PL330 Technical Reference Manual state machine for axi to apb bridge pl330 dma AMBA AXI
Text: CoreLink DMA Controller DMA-330 Revision: r1p1 Technical Reference Manual Copyright 2007, 2009-2010 ARM Limited. All rights reserved. ARM DDI 0424C ID080710 CoreLink DMA Controller DMA-330 Technical Reference Manual Copyright © 2007, 2009-2010 ARM Limited. All rights reserved.
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DMA-330
0424C
ID080710)
32-bit
ID080710
DMA Controller DMA-330 Supplement to AMBA Designer ADR-301 User Guide
adr-301
DMA-330
AMBA AXI dma controller designer user guide
armv7-a
dma 330 user guide pl330
DMA Controller PL330 Technical Reference Manual
state machine for axi to apb bridge
pl330 dma
AMBA AXI
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82371SB
Abstract: 430fx 430-FX
Text: 82371FB PIIX AND 82371 SB (PIIX3) PCI ISA IDE XCELERATOR Bridge Between the PCI Bus and ISA Bus • Enhanced DMA Functions — Two 8237 DMA Controllers — Fast Type F DMA — Compatible DMA Transfers — 7 Independently Programmable Channels ■ X-Bus Peripheral Support
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82371FB
82371SB
430fx
430-FX
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EP660
Abstract: No abstract text available
Text: Eureka Technology EP660 DMA Controller FEATURES • Multiple independent DMA modules • Up to 16 DMA channels supported • Designed for ASIC or FPGA implementations in various system environments • Two types of DMA modules for memory memory and memory - I/O data transfer.
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EP660
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TXC10
Abstract: RxD10 RXC10 "Content Addressable Memory" LXT970A MB86961A MB86974 TXEN10 tpip IS 2076-31
Text: 10/100 Mbps Ethernet Controller MB86974 PCI BUS INTERFACE and DMA MAC LAYER DMA Transmit FIFO PHYSICAL LAYER MAC Tx FIFO Transmit Block System Block Diagram P C I DMA Engine D I I Flow Control DMA Receive FIFO Address CAM Command and Status Registers M I I
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MB86974
25MHz
LAN-FS-20763-1/99
TXC10
RxD10
RXC10
"Content Addressable Memory"
LXT970A
MB86961A
MB86974
TXEN10
tpip
IS 2076-31
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MEP core
Abstract: 0X1015 transistor B1010 64Bytes MeP-c4 Toshiba MeP
Text: User’s Manual Data Streamer DMA Controller/Local Bus Unit User’s Manual Data Streamer (DMA Controller/Local Bus Unit) User’s Manual Data Streamer (DMA Controller/Local Bus Unit) User’s Manual Semiconductor Company MEPUM03003-E24 i Data Streamer (DMA Controller/Local Bus Unit) User’s Manual
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MEPUM03003-E24
MEP core
0X1015
transistor B1010
64Bytes
MeP-c4
Toshiba MeP
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design of dma controller using vhdl
Abstract: FPGA based dma controller using vhdl timing diagram of DMA Transfer CY39100V676-200MBC
Text: Microprocessor Peripherals FPGA/CPLD IP Inventra DMAx1-B1 DMA Controller FISPbus INTERFACE DMA_END DMA A REGISTER INTERFACE FISPbus INTERFACE D FTS FTR DMAx1-B1 IR 2 DMA B SYSTEM DMA_REQ A S H E E T DMAx1-B1 key features: • Single-channel DMA controller with
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destinati000
PD-62301
001-FO
design of dma controller using vhdl
FPGA based dma controller using vhdl
timing diagram of DMA Transfer
CY39100V676-200MBC
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Intel 8237 dma controller block diagram
Abstract: C8237 3S50-5 Intel 8237 16 bit register in verilog BIT20
Text: Four, independent DMA channels Enable/Disable control of individual DMA requests C8237 Independent auto-initialization of all channels Programmable DMA Controller Xilinx Core Memory-to-Memory transfers Memory block initialization Address increment of decrement
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C8237
C8237
Intel 8237 dma controller block diagram
3S50-5
Intel 8237
16 bit register in verilog
BIT20
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C8237
Abstract: Block Diagram of 8237
Text: Enable/Disable control of individual DMA requests Four, independent DMA channels C8237 Independent auto-initialization of all channels Programmable DMA Controller Altera Core Memory-to-Memory transfers Memory block initialization Address increment of decrement
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C8237
C8237
EP2S60-3
Block Diagram of 8237
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Intel 8237A
Abstract: intel 8237A DMA Controller 231369 8237A-5
Text: Intel 8237A HIGH PERFORMANCE PROGRAMMABLE DMA CONTROLLER 8237A-5 • Enable/Disable Control of Individual DMA Requests ■ Four Independent DMA Channels ■ Independent Autoinitialization of All Channels ■ Memory-to-Memory Transfers ■ Memory Block Initialization
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237A-5)
40-Lead
237A-5
DNE02
Intel 8237A
intel 8237A DMA Controller
231369
8237A-5
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tc001
Abstract: Am2940
Text: Am2940 DMA Address Generator DISTINCTIVE CHARACTERISTICS DMA Address Generation Programmable Control Modes Generates memory address, word count and DONE signal for DMA transfer operation. Provides four types of DMA transfer control plus memory address increm ent/decrem ent.
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Am2940
Am2940
03575B
tc001
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SB013
Abstract: STP2012 53c90 NCR
Text: S un M icro electro nics July 1997 DMA2 DATA SHEET SBus DMA Controller D e s c r ip t io n The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AMD Am7990 Local Area Network Control
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STP2012
Am7990
53C90
STP2012
SB013
53c90 NCR
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TRISCEND
Abstract: Fast-Chip E520 AN-22 AN32 APP305-0022-001 app abstract
Text: Using the E5 Embedded DMA Controller July 2001 AN-22 Abstract This application note describes how to use the DMA feature of the E5 by working through example designs. Contents Using the E5 Embedded DMA
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AN-22
APP305-0022-001
25-JUN-2001
TRISCEND
Fast-Chip
E520
AN-22
AN32
APP305-0022-001
app abstract
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TMS320C5000
Abstract: TMS320C5000 structure TMS320C54x, instruction set C5000 SPRU131 SPRU302
Text: Application Report SPRA641 - March 2000 TMS320C5000 DMA Applications Ramesh A. Iyer DSP West Applications ABSTRACT A Direct Memory Access DMA controller is available on select members of the TMS320C5000 family of digital signal processors (DSPs). The DMA controller is used to
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SPRA641
TMS320C5000
TMS320C5000 structure
TMS320C54x, instruction set
C5000
SPRU131
SPRU302
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OTAQ
Abstract: bma 023 DS32N Bull Micral of America data of car driving licence holders 000D AZ9011 Car Central lock system TDI A29011
Text: A Z 9011 Bus Master DMA Controller* Introduction The AZ9011 provides eight channels of Direct Memory Access DMA . The system microprocessor programs the DMA registers via the Micro Channel* for the various modes of operation, transfer addresses and transfer
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AZ90H
AZ9011
programm25
AZ9011
12/iaÂ
OTAQ
bma 023
DS32N
Bull Micral of America
data of car driving licence holders
000D
Car Central lock system TDI
A29011
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53C90A
Abstract: ncr53c90 STP2012 53C90 AD12 AM7990 STP2013 EIRQ15 STP2011 53c90 scsi
Text: STP2012QFP July 1997 DMA2 DATA SHEET SBus DMA Controller DESCRIPTION The STP2012 SBus DMA Controller DMA2 provides three channels for DMA transfers over the SBus. It has three external interfaces designed to provide DMA access to one AMD Am7990 Local Area Network Controller for the Ethernet (LANCE), one NCR 53C90 SCSI controller (ESP), and one programmable Centronics-type parallel port. The
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STP2012QFP
STP2012
Am7990
53C90
STP2012PQFP
160-Pin
STP2012
53C90A
ncr53c90
AD12
STP2013
EIRQ15
STP2011
53c90 scsi
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GPIB-1014
Abstract: GPIB-1014-1S-EH PD7210 1014D GPIB-1014-1
Text: DMA GPIB Interfaces for VMEbus GPIB-1014, GPIB-1014D GPIB-1014, GPIB-1014D Complete IEEE 488 Talker/Listener/Controller DMA transfers Rates up to 500 kbytes/s Unlimited data block lengths Full 24-bit addressing GPIB synchronization detection General-purpose DMA capability
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GPIB-1014,
GPIB-1014D
24-bit
GPIB-1014
32-bit
NI-488M
GPIB-1014-1/EH/1S
GPIB-1014
GPIB-1014-1S-EH
PD7210
1014D
GPIB-1014-1
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AN10040
Abstract: ISP1761 ISP1582
Text: AN10040 ISP1761 Peripheral DMA Initialization Rev. 01 — 7 September 2004 Application note Document information Info Content Keywords isp1761, usb, universal serial bus, dma Abstract This document explains the registers that are involved when using DMA on the peripheral controller of ISP1761.
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AN10040
ISP1761
isp1761,
ISP1761.
AN10040
ISP1582
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intel 8237A DMA Controller
Abstract: 231369 8237A-5 8237A transfer modes order 231369
Text: inU. 8237A HIGH PERFORMANCE PROGRAMMABLE DMA CONTROLLER 8237A-5 • ■ ■ ■ ■ ■ ■ ■ Enable/Disable Control of Individual DMA Requests Four Independent DMA Channels Independent Autoinitialization of All Channels Memory-to-Memory Transfers Memory Block Initialization
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237A-5)
237A-5
40-Lead
intel 8237A DMA Controller
231369
8237A-5
8237A transfer modes
order 231369
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TMS320C5000
Abstract: TMS320C5000 structure C5000 SPRU131 SPRU302
Text: Application Report SPRA641 - March 2000 TMS320C5000 DMA Applications Ramesh A. Iyer DSP West Applications ABSTRACT A Direct Memory Access DMA controller is available on select members of the TMS320C5000 family of digital signal processors (DSPs). The DMA controller is used to
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SPRA641
TMS320C5000
TMS320C5000 structure
C5000
SPRU131
SPRU302
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