DPRAM
Abstract: verilog code for 16 kb ram block code error management, verilog APEX20K APEX20KC APEX20KE CRC-32 802.3 CRC32 crc 16 verilog STATIC RAM vhdl
Text: DMAC Media Access Controller ver 2.07 OVERVIEW The DMAC is hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external PHY device enables network functionality in design. It is capable of transmitting
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DPRAM
verilog code for 16 kb ram
block code error management, verilog
APEX20K
APEX20KC
APEX20KE
CRC-32
802.3 CRC32
crc 16 verilog
STATIC RAM vhdl
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0E000000
Abstract: AR-S1 26
Text: APPLICATION NOTE H8SX Family DMAC Offset Transfer Preliminary Summary Image data is rotated 90 degrees to the left using DMAC offset transfer. Contents 1. Specifications . 2
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REJ06B0300-0100O/Rev
0E000000
AR-S1 26
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DTC Data Technology
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2200 Series Simultaneous Startup of DTC, DMAC, and CPU Introduction Starts up DTC, DMAC, and CPU each time a compare match occurs. DTC transfers data from the ROM to the I/O port and outputs pulses. The DMAC transfers data stored in RAM1 to RAM2. The CPU monitors the state of the port and
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H8S/2200
H8S/2239
REJ06B0323-0100Z/Rev
DTC Data Technology
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sfr32c83
Abstract: No abstract text available
Text: APPLICATION NOTE M32C/80 Series Using DMAC II Single Transfer 1. Abstract This application note describes how to use DMAC II in single transfer mode. 2. Introduction The explanation of this issue is applied to the following condition: Applicable MCU: M32C/80 Series
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M32C/80
M32C/85
REJ05B0508-0100/Rev
sfr32c83
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cpu in diagrams
Abstract: No abstract text available
Text: APPLICATION NOTE H8S Family Simultaneous Startup of DTC, DMAC, and CPU Introduction Starts up DTC, DMAC, and CPU each time a compare match occurs. DTC transfers data from the ROM to the I/O port and outputs pulses. The DMAC transfers data stored in RAM1 to RAM2. The CPU monitors the state of the port and
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H8S/2339
REJ06B0470-0100/Rev
cpu in diagrams
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100C
Abstract: SH7670 DARN
Text: APPLICATION NOTE SH7670 Group Using the DMAC to Transfer Data between Memory Areas Introduction This application note provides an example of transferring data between memory areas with the direct memory access controller DMAC of the SH7670. Target Device
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SH7670
SH7670.
SH7670
REJ06B0793-0100/Rev
100C
DARN
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Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8SX Family Ring Buffer Processing by DMAC Extended Repeat Area Function Preliminary Summary Ring buffer processing is performed by means of the DMAC extended repeat area function. Contents 1. Specifications . 2
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REJ06B0301-0100O/Rev
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h8sx
Abstract: No abstract text available
Text: APPLICATION NOTE H8SX Family Using the DMAC to Drive Continuous SCI Transmission in Asynchronous Mode Introduction Asynchronous transfer is used to transmit 128 bytes of data. Using the DMAC to handle the transfer transmission of data enables continuous transmission with no CPU intervention.
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H8SX/1653
REJ06B0665-0100/Rev
h8sx
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UART0
Abstract: f1SIO
Text: APPLICATION NOTE M16C/62P Group Procedure for Successive Serial I/O Transmission/Reception Using the DMAC 1. Abstract This application note presents the procedure for successive serial I/O transmission/reception using the DMAC and an example on how to use it.
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M16C/62P
REJ05B0590-0101/Rev
UART0
f1SIO
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FFA000
Abstract: No abstract text available
Text: APPLICATION NOTE H8SX Family Ring Buffer Processing Using Extended Repeat Area Function of the DMAC Introduction The direct memory access controller DMAC performs ring buffer processing using the extended repeat area function. Target Device H8SX/1653 Contents
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H8SX/1653
REJ06B0623-0100/Rev
FFA000
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0C00
Abstract: 100C
Text: APPLICATION NOTE SH7211 Group Data Transfer between Memory Areas with DMAC Introduction This application note provides an example of transferring data between memory areas with the direct memory access controller DMAC of the SH7211. Target Device SH7211
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SH7211
SH7211.
SH7211
REJ06B0724-0101/Rev
0C00
100C
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Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE M16C/26 Using the DMAC with a Forward Destination 1.0 Abstract The following article introduces and shows an example of how to use the DMAC function of the M16C/26 with a fixed source address and forward counting destination address. 2.0 Introduction
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M16C/26
M16C/26
M30262
16-bit
M16C/60
10-bit
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NC30
Abstract: No abstract text available
Text: APPLICATION NOTE M16C/62 Using the M16C/62 DMAC in Forward Destination Mode 1.0 Abstract The following article introduces and shows an example of how to use the DMAC function of the M16C/62 with a fixed source address and forward counting destination address.
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M16C/62
M16C/62
16-bit
NC30
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NC30
Abstract: No abstract text available
Text: APPLICATION NOTE M16C/62 Using the M16C/62 DMAC in Forward Source Mode 1.0 Abstract The following article introduces and shows an example of how to use the DMAC function of the M16C/62 with a forward counting source address and fixed destination address. 2.0 Introduction
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M16C/62
M16C/62
16-bit
NC30
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SH7263
Abstract: 101C SH7203 iodefine CBR4800
Text: APPLICATION NOTE SH7263/SH7203 Group Data Transfer to On-chip Peripheral Modules with DMAC Introduction This application note provides an example of transferring data to on-chip peripheral modules with the direct memory access controller DMAC of the SH7263/SH7203.
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SH7263/SH7203
SH7263/SH7203.
SH7263/SH7203
REJ06B0734-0101/Rev
SH7263
101C
SH7203
iodefine
CBR4800
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101C
Abstract: 9600BPS
Text: APPLICATION NOTE SH7211 Group Data Transfer to On-chip Peripheral Modules with DMAC Introduction This application note provides an example of transferring data to on-chip peripheral modules with the direct memory access controller DMAC of the SH7211. Target Device
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SH7211
SH7211.
SH7211
REJ06B0725-0101/Rev
101C
9600BPS
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PFC 32U
Abstract: 101C SH7670 115200 UART
Text: APPLICATION NOTE SH7670 Group Using the DMAC to Transfer Data to On-chip Peripheral Modules Introduction This application note provides an example of transferring data to on-chip peripheral modules with the direct memory access controller DMAC of the SH7670.
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SH7670
SH7670.
SH7670
REJ06B0794-0100/Rev
PFC 32U
101C
115200 UART
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FFFE0010
Abstract: FFFE0018 FFFE1000 FFFE1004 FFFE1008 FFFE100C H1-303
Text: APPLICATION NOTE SH7211 Group Data Transfer between On-chip RAM Areas with DMAC Burst Mode Introduction This application note describes the operation of the DMAC, and is intended for reference to help in the design of user software. Target Device SH7211
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SH7211
SH7211
REJ06B0721-0100/as
REJ06B0721-0100/Rev
FFFE0010
FFFE0018
FFFE1000
FFFE1004
FFFE1008
FFFE100C
H1-303
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0C00
Abstract: 100C SH7286
Text: APPLICATION NOTE SH7280 Group Data Transfer between Memory Areas with DMAC Introduction This application note provides an example of transferring data between memory areas with the direct memory access controller DMAC of the SH7285. Target Device SH7285
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SH7280
SH7285.
SH7285
REJ06B0768-0100/Rev
0C00
100C
SH7286
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h8sx
Abstract: No abstract text available
Text: APPLICATION NOTE H8SX Family Using the DMAC to Drive Continuous SCI Reception in Asynchronous Mode Introduction Asynchronous transfer is used to receive 128 bytes of data. Using the DMAC to handle the transfer reception of data enables continuous reception with no CPU intervention.
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H8SX/1653
REJ06B0666-0100/Rev
h8sx
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MD10
Abstract: MD11
Text: APPLICATION NOTE M32C/85 Group Procedure for Successive Serial I/O Transmission/Reception Using the DMAC 1. Abstract This application note presents the procedure for successive serial I/O transmission/reception using the DMAC and an example on how to use it.
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M32C/85
REJ05B0506-0101/Rev
MD10
MD11
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Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE M16C/Tiny Series Operation of DMAC One-Shot Transfer Mode 1. Abstract In one-shot transfer mode of DMAC, choose functions from those listed in Table 1. Operations of the checked items are described below. Table 1. Choosed Functions Item
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M16C/Tiny
M16C/26,
M16C/26A,
M16C/28,
M16C/29
REJ05B0633-0100/Rev
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hd68000
Abstract: No abstract text available
Text: -U172.1 HD63450, HD63450Y, HD63450P HD63450PS, HD63450CP Ci CMOS Direct Memory Access Controller SEPTEMBER, 1989 0 H IT A C H I The HD63450 is a CMOS Direct Memory Access Controller DMAC . It is upwardly compatible with the NMOS DMAC HD68450. In addition to the NMOS DMAC HD68450 features, the
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-U172
HD63450,
HD63450Y,
HD63450P
HD63450PS,
HD63450CP
HD63450
HD68450.
HD68450
hd68000
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WE32104
Abstract: we32100 DMAC
Text: WE 32104 DMA Controller Description The WE 32104 DMA Controller DMAC is a memory-mapped peripheral device that performs memory-to-memory, memory fill, memory-to-peripheral, and peripheral-tomemory data transfers quickly and efficiently. The DMAC contains specialized hardware that
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32-bit
133-pin
225pF)
WE32104
we32100
DMAC
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