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    IndustrialeMart KMSR-DS1004

    SSR RELAY SPST-NO 100A 90-480V
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    DigiKey KMSR-DS1004 Box 2 1
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    Rochester Electronics LLC DS1004Z-4

    5-TAP HIGH SPEED DELAY LINE
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    DigiKey DS1004Z-4 Tube 27
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    Maxim Integrated Products DS1004Z-4

    IC DELAY LINE 5TAP 21NS 8SOIC
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    DigiKey DS1004Z-4 Tube
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    Rochester Electronics DS1004Z-4 2,293 1
    • 1 $11.05
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    Rochester Electronics LLC DS1004Z-3

    5-TAP HIGH SPEED DELAY LINE
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    DigiKey DS1004Z-3 Tube 27
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    Maxim Integrated Products DS1004Z-3

    IC DELAY LINE 5TAP 17NS 8SOIC
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    DigiKey DS1004Z-3 Tube
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    Rochester Electronics DS1004Z-3 8,105 1
    • 1 $11.05
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    Find more DS1004 price and stock on Findchips.com

    DS1004 Datasheets (51)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    DS1004 Dallas Semiconductor 5-Tap High Speed Silicon Delay Line Original PDF
    DS1004 Maxim Integrated Products 5-Tap High-Speed Silicon Delay Line Original PDF
    DS1004C-302 Maxim Integrated Products 5-Tap High-Speed Silicon Delay Line Original PDF
    DS1004C-302/T&R Maxim Integrated Products 5-Tap High-Speed Silicon Delay Line Original PDF
    DS1004C-303 Maxim Integrated Products 5-Tap High-Speed Silicon Delay Line Original PDF
    DS1004C-303/T&R Maxim Integrated Products 5-Tap High-Speed Silicon Delay Line Original PDF
    DS1004C-305 Maxim Integrated Products 5-Tap High-Speed Silicon Delay Line Original PDF
    DS1004M Maxim Integrated Products Delay Line, 5-Tap High Speed Silicon Delay Line Original PDF
    DS1004M Dallas Semiconductor 5-Tap High Speed Silicon Delay Line Scan PDF
    DS1004M Dallas Semiconductor 5-Tap High-Speed Silicon Delay Line Scan PDF
    DS1004M Dallas Semiconductor 5-Tap High Speed Silicon Delay Line Scan PDF
    DS1004M-2 Dallas Semiconductor 5-Tap High Speed Silicon Delay Line Original PDF
    DS1004M-2 Maxim Integrated Products Delay Line, Active Tapped, 5 Tap, 13nSec Delay, 5V Supply Voltage, 8-DIP Original PDF
    DS1004M-3 Dallas Semiconductor 5-Tap High Speed Silicon Delay Line Original PDF
    DS1004M-3 Maxim Integrated Products Delay Line, Active Tapped, 5 Tap, 17nSec Delay, 5V Supply Voltage, 8-DIP Original PDF
    DS1004M-4 Dallas Semiconductor 5-Tap High Speed Silicon Delay Line Original PDF
    DS1004M-5 Dallas Semiconductor 5-Tap High Speed Silicon Delay Line Original PDF
    DS1004Z Dallas Semiconductor 5-Tap High-Speed Silicon Delay Line Original PDF
    DS1004Z Dallas Semiconductor 5-Tap High Speed Silicon Delay Line Scan PDF
    DS1004Z Dallas Semiconductor 5-Tap High-Speed Silicon Delay Line Scan PDF

    DS1004 Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    DS1425L-F5

    Abstract: rtc ds1307 dallas ds2501 dallas ds2501 Datasheet dallas ds1280 DS2501 ds1642-150 DS1669 replacement ds2501 Datasheet DS1608S
    Text: ORDERING INFORMATION DEVICE DS0621–SDK DS0630 DS1000 DS1000–IND DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1013 DS1020 DS1021 DS1033 DS1035 DS1040 PACKAGE TYPE Software Software 14–Pin DIP 8–Pin DIP 16–Pin SOIC 8–Pin SOIC 8–Pin DIP 8–Pin SOIC


    Original     		PDF DS0621 DS0630 DS1000 DS1000 DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1425L-F5 rtc ds1307 dallas ds2501 dallas ds2501 Datasheet dallas ds1280 DS2501 ds1642-150 DS1669 replacement ds2501 Datasheet DS1608S

    pt45

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.2, June 2006 LatticeSC Family Data Sheet Introduction June 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 110mW VCC12. LFSC25 900-Ball pt45

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC/M Family Data Sheet DS1004 Version 02.1, June 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.4b, February 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW SC115

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC/M Family Data Sheet DS1004 Version 01.6, August 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW

    2-bit comparator

    Abstract: LFSC3GA15E-5F900I PR77A PR55D pr94a diode transistor pt36c pt36C PB110C pb127d PB138
    Text: LatticeSC/M Family Data Sheet DS1004 Version 01.8, November 2007 LatticeSC/M Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW 2-bit comparator LFSC3GA15E-5F900I PR77A PR55D pr94a diode transistor pt36c pt36C PB110C pb127d PB138

    Untitled

    Abstract: No abstract text available
    Text: DS1004 5-Tap High Speed Silicon Delay Line www.dalsemi.com FEATURES PIN ASSIGNMENT All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances of ±1.5 ns


    Original     		PDF DS1004 DS1004M 300-mil) DS1004Z 150-mil) 56-G2008-001C DS1004Z-3 DS1004Z-4 DS1004Z-5 DS1004Z-5+

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.5, March 2007 LatticeSC Family Data Sheet Introduction March 2007 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW LFSC25 FF1020 LFSC80

    Ablebond 71

    Abstract: 9727
    Text: 08/08/2002 RELIABILITY REPORT FOR DS1004, Rev E1 Dallas Semiconductor 4401 South Beltwood Parkway Dallas, TX 75244-3292 Prepared by: Ken Wendel Reliability Engineering Manager Dallas Semiconductor 4401 South Beltwood Pkwy. Dallas, TX 75244-3292 Email : [email protected]


    Original     		PDF DS1004, reliabilit235C DS1004 DS1000 Ablebond 71 9727

    PB68C

    Abstract: LFSCM3GA40EP1
    Text: LatticeSC Family Data Sheet DS1004 Version 01.4a, January 2007 LatticeSC Family Data Sheet Introduction November 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW LVPECL33 SC115 PB68C LFSCM3GA40EP1

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC Family Data Sheet DS1004 Version 01.3, August 2006 LatticeSC Family Data Sheet Introduction August 2006 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 110mW

    pb127d

    Abstract: No abstract text available
    Text: LatticeSC/M Family Data Sheet DS1004 Version 02.2, December 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW pb127d

    Untitled

    Abstract: No abstract text available
    Text: LatticeSC/M Family Data Sheet DS1004 Version 01.9, January 2008 LatticeSC/M Family Data Sheet Introduction January 2008 Preliminary Data Sheet DS1004 Features • High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 132 to 942 I/Os


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW

    DS1669-100

    Abstract: TQFP 100 pin Socket 4 pin dip switch DS2401 PACKAGE 16 pin DIP socket DS1804 NV 2 pin dip switch ds1232(ind) data sheet ds1642-150 DS1620S
    Text: ORDERING INFORMATION DEVICE DS0621–SDK DS1000 DS1000–IND DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1013 DS1020 DS1021 DS1033 DS1035 DS1040 PACKAGE TYPE Software 14–Pin DIP 8–Pin DIP 16–Pin SOIC 8–Pin SOIC 8–Pin DIP 8–Pin SOIC 14–Pin DIP


    Original     		PDF DS0621 DS1000 DS1000 DS1003 DS1004 DS1005 DS1007 DS1010 DS1012 DS1013 DS1669-100 TQFP 100 pin Socket 4 pin dip switch DS2401 PACKAGE 16 pin DIP socket DS1804 NV 2 pin dip switch ds1232(ind) data sheet ds1642-150 DS1620S

    Untitled

    Abstract: No abstract text available
    Text: DS1004 5-Tap High Speed Silicon Delay Line www.dalsemi.com PIN ASSIGNMENT FEATURES All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances of ±1.5 ns


    Original     		PDF DS1004 DS1004M 300-mil)

    PB110C

    Abstract: PB124A pt36C SCM15 BA5 904 AF P PL80B PR55D pr94a diode transistor pt36c transistor pt42c
    Text: LatticeSC/M Family Data Sheet DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 Features – 1 to 7.8 Mbits memory – True Dual Port/Pseudo Dual Port/Single Port – Dedicated FIFO logic for all block RAM


    Original     		PDF DS1004 DS1004 500MHz 700MHz 600Mbps 125Gbps) 1A-10 1152-ball 1704-ball PB110C PB124A pt36C SCM15 BA5 904 AF P PL80B PR55D pr94a diode transistor pt36c transistor pt42c

    PB97A

    Abstract: PR45C pr77a
    Text: LatticeSC/M Family Data Sheet DS1004 Version 02.4, December 2011 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 Features  High Performance FPGA Fabric • 15K to 115K four input Look-up Tables LUT4s • 139 to 942 I/Os • 700MHz global clock; 1GHz edge clocks


    Original     		PDF DS1004 DS1004 700MHz 600Mbps 125Gbps) 105mW 1A-10 1152-ball 1704-ball PB97A PR45C pr77a

    DS1004

    Abstract: DS1004M DS1004M-2 DS1004M-3 DS1004M-4 DS1004M-5 DS1004Z DS1004Z-2 DS1004Z-3 DS1004Z-4
    Text: DS1004 5-Tap High Speed Silicon Delay Line www.dalsemi.com FEATURES PIN ASSIGNMENT All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances of ±1.5 ns


    Original     		PDF DS1004 DS1004M 300-mil) DS1004 DS1004M-2 DS1004M-3 DS1004M-4 DS1004M-5 DS1004Z DS1004Z-2 DS1004Z-3 DS1004Z-4

    PB80D

    Abstract: PR87A PR98A PR96A PB110C pr94a diode pt36C pr77a transistor pt36c transistor pt42c
    Text: LatticeSC/M Family Data Sheet DS1004 Version 02.3, January 2010 LatticeSC/M Family Data Sheet Introduction January 2010 Data Sheet DS1004 Features – 1 to 7.8 Mbits memory – True Dual Port/Pseudo Dual Port/Single Port – Dedicated FIFO logic for all block RAM


    Original     		PDF DS1004 DS1004 500MHz 700MHz 600Mbps 125Gbps) 1A-10 1152-ball 1704-ball PB80D PR87A PR98A PR96A PB110C pr94a diode pt36C pr77a transistor pt36c transistor pt42c

    DS1004

    Abstract: DS1004M DS1004M-2 DS1004M-3 DS1004M-4 DS1004M-5 DS1004Z DS1004Z-2 DS1004Z-3 DS1004Z-4
    Text: Ì DS1004 5-Tap High Speed Silicon Delay Line WÈ w mmmommtm www.dalsemi.com PIN ASSIGNMENT FEATURES All-silicon timing circuit Five equally delayed clock phases per input Precise tap-to-tap delay tolerances of ±0.5, ±0.75, or ±1 ns Input-to-tap 1 delay of 5 ns


    OCR Scan     		PDF DS1004 DS1004M 300-mil) DS1004Z DS1004M-2 DS1004M-3 DS1004M-4 DS1004M-5 DS1004Z-2 DS1004Z-3 DS1004Z-4

    Untitled

    Abstract: No abstract text available
    Text: D S1004 n A I I A C DS1004 5-Tap High-Speed Silicon Delay Line s e m ic o n d u c to r PIN ASSIGNMENT FEATURES • All-silicon timing circuit • Five equally delayed clock phases per input • Precise tap-to-tap delay tolerances of ±0.5, +0.75, or ±1 ns


    OCR Scan     		PDF S1004 DS1004 DS1004M 0Dlb23fi

    DS1004

    Abstract: DS1004M DS1004M-2 DS1004M-3 DS1004M-4 DS1004M-5 DS1004Z DS1004Z-2 DS1004Z-3 DS1004Z-4
    Text: DS 1004 DALLAS SEMICONDUCTOR DS1004 5-Tap High-Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon timing circuit IN C • Five equally delayed clock phases per input • Precise ta p -to -tap delay tolerances of ±0.5, ±0.75, or ±1 ns Z l Vcc


    OCR Scan     		PDF DS1004 DS1004M DS1004 DS1004M-2 DS1004M-3 DS1004M-4 DS1004M-5 DS1004Z DS1004Z-2 DS1004Z-3 DS1004Z-4

    Untitled

    Abstract: No abstract text available
    Text: D S 1004 DALLAS SEMICONDUCTOR DS1004 5-Tap High-Speed Silicon Delay Line FEATURES PIN ASSIGNMENT • All-silicon timing circuit • Five equally delayed clock phases per input • Precise tap-to-tap delay tolerances of ±0.5, ±0.75, or ±1 ns IN L 1 8 □


    OCR Scan     		PDF DS1004 DS1004M

    DS1004Z-004

    Abstract: No abstract text available
    Text: DS1004 DALLAS SEMICONDUCTOR DS1004 5-Tap High-Speed Silicon Delay Line PIN ASSIGNMENT FEATURES • All-silicon timing circuit • Five equally delayed clock phases per input • Precise tap-to-tap delay tolerances of ±0.5, ±0.75, or ±1 ns IN C 1 TAP 2 [ I


    OCR Scan     		PDF DS1004 DS1004M DS1004Z-004