FFB000
Abstract: No abstract text available
Text: APPLICATION NOTE H8SX Family DTC Transfer with Transfer Information Read Skipping Processing Introduction The data transfer controller DTC is activated by an IRQ0 interrupt and transfers 64 bytes of data twice. In the second data transfer, the DTC skips reading of the transfer information.
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H8SX/1653
REJ06B0624-0100/Rev
FFB000
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FFB000
Abstract: No abstract text available
Text: APPLICATION NOTE H8SX Family DTC Transfer with Transfer Information Write-Back Skipping Processing Introduction The data transfer controller DTC is activated by an IRQ0 interrupt and transfers two bytes of data. In the second byte transfer, the DTC skips write-back of the transfer information.
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H8SX/1653
REJ06B0625-0100/Rev
FFB000
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Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2200 Series DTC Transfer Activation by 8-Bit Timer Channel 0A Interrupt, Examples of Using Chain Function Introduction Transfers data on an SRAM chip to other addresses on the chip with the DTC that is activated by the 8-bit timer channel 0A interrupt. It also transfers data continuously to other addresses on the SRAM chip with the DTC chain
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H8S/2200
H8S/2215
REJ06B0349-0100Z/Rev
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R5F70865
Abstract: No abstract text available
Text: APPLICATION NOTE SH7080 Group Data Transfer Controller DTC in Chain Transfer Mode Introduction This application note describes the chain transfer mode of the data transfer controller (DTC). It is intended as reference material to help in the design of user software.
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SH7080
SH7086
REJ06B0703-0100/Rev
R5F70865
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DTC Data Technology
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2200 Series Simultaneous Startup of DTC, DMAC, and CPU Introduction Starts up DTC, DMAC, and CPU each time a compare match occurs. DTC transfers data from the ROM to the I/O port and outputs pulses. The DMAC transfers data stored in RAM1 to RAM2. The CPU monitors the state of the port and
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H8S/2200
H8S/2239
REJ06B0323-0100Z/Rev
DTC Data Technology
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H0011
Abstract: FFB000 DTC Data Technology
Text: APPLICATION NOTE H8SX Family DTC Data Transfer Initiated by IRQ Interrupt Introduction The DTC is activated by an IRQ interrupt and it performs data transfer of 128 bytes. Target Device H8SX/1582F Contents 1. Specifications . 2
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H8SX/1582F
REJ05B0789-0100/Rev
H0011
FFB000
DTC Data Technology
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h8sx
Abstract: No abstract text available
Text: APPLICATION NOTE H8SX Family DTC Block Transfer Introduction This application note describes using the data transfer controller DTC function to transfer five blocks of data, each comprising two bytes, and outputting the transferred data to I/O ports (P1 and P2).
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H8SX/1663
H8SX/1622
H8SX/1638
H8SX/1648
H8SX/1648A
H8SX/1648L
H8SX/1648G
REJ06B0816-0100/Rev
h8sx
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cpu in diagrams
Abstract: No abstract text available
Text: APPLICATION NOTE H8S Family Simultaneous Startup of DTC, DMAC, and CPU Introduction Starts up DTC, DMAC, and CPU each time a compare match occurs. DTC transfers data from the ROM to the I/O port and outputs pulses. The DMAC transfers data stored in RAM1 to RAM2. The CPU monitors the state of the port and
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H8S/2339
REJ06B0470-0100/Rev
cpu in diagrams
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2215S
Abstract: 0x600000
Text: APPLICATION NOTE H8S/2200 Series DTC Transfer Software Activation Introduction Transfers data on an SRAM chip to other addresses on the chip by DTC that is activated by software. Target Device H8S/2215 Contents 1. Overview . 2
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H8S/2200
H8S/2215
REJ06B0348-0100Z/Rev
2215S
0x600000
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R5F70865
Abstract: No abstract text available
Text: APPLICATION NOTE SH7080 Group Data Transfer Controller DTC in Repeat Transfer Mode Introduction This application note describes the repeat transfer mode of the data transfer controller (DTC). It is intended as reference material to help the design of user software.
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SH7080
SH7086
REJ06B0701-0100/Rev
R5F70865
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R5F7085
Abstract: SH7085 DTCE10
Text: APPLICATION NOTE SH7080 Group SCIF Asynchronous Serial Data Transfer Function Using the DTC Introduction This application note describes data transmission and reception that uses the internal SCIF Serial Communication Interface with FIFO for asynchronous serial transfer and a data transfer function that uses the internal DTC (Data
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SH7080
SH7085
R5F7085)
REJ05B0738-0100
R5F7085
SH7085
DTCE10
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DSP DTS
Abstract: R5F70865
Text: APPLICATION NOTE SH7080 Group Data Transfer Controller DTC in Block Transfer Mode Introduction This application note describes the block transfer mode of the data transfer controller (DTC). It is intended as reference material to help in the design of user software.
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SH7080
SH7086
REJ06B0702-0100/Rev
DSP DTS
R5F70865
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R5F70865
Abstract: No abstract text available
Text: APPLICATION NOTE SH7080 Group Data Transfer Controller DTC in Normal Transfer Mode Introduction This application note describes the normal transfer mode of the data transfer controller (DTC). It is intended as reference material to help in design of user software.
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SH7080
SH7086
REJ06B0700-0100/Rev
R5F70865
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SH7145
Abstract: No abstract text available
Text: APPLICATION NOTE SH7145 Group I2C Bus Interface in Combined Use with DTC Introduction This application note describes how to implement automatic execution of transmission and reception of data via the I2C bus Inter IC Bus interface through the use of DTC (Data Transfer Controller) of the SH7145F. The master device is
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SH7145
SH7145F.
SH7145F,
SH7145F
REJ06B0399-0100Z/Rev
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CKE 8002
Abstract: No abstract text available
Text: APPLICATION NOTE SH7280 Group Using the DTC in the Asynchronous-Mode Transfer of Serial Data by the SCI Introduction This application note describes the transfer of serial data in asynchronous mode by the serial communications interface SCI with the aid of the data-transfer controller (DTC). This application note is a summary for quick reference of
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SH7280
SH7285
REJ06B0775-0100/Rev
CKE 8002
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2215S
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2200 Series DTC Transfer Activation by Bit Timer Channel 0A Interrupt, Examples of Using the Normal Mode Introduction Transfers data on an SRAM chip to other addresses on the chip with DTC that is activated by the 8-bit timer channel
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H8S/2200
H8S/2215
REJ06B0350-0100Z/Rev
2215S
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Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE SH7280 Group Using the DTC in the Asynchronous-Mode Transfer of Serial Data by the SCIF Introduction This application note describes the transfer of serial data in asynchronous mode by the serial communications interface with FIFO SCIF with the aid of the data-transfer controller (DTC). This application note is a summary for quick
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SH7280
SH7285
REJ06B0846-0100/Rev
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PO16
Abstract: 1648l
Text: APPLICATION NOTE H8SX Family PPG Non-Overlapping Unit 1 – DTC Transfer – Introduction This application note describes using the non-overlapping operation mode of the programmable pulse generator (PPG) function to produce pulse output. In addition, the data transfer controller (DTC) is used to transfer the next unit of data
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H8SX/1648
H8SX/1648A
H8SX/1648L
H8SX/1648G
H8SX/1648H
REJ06B0813-0100/Rev
PO16
1648l
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Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE SH7280 Group Using the DTC in the Clock Synchronous-Mode Transfer of Serial Data by the SCI Introduction This application note describes the transfer of serial data in clock synchronous mode by the serial communications interface SCI with the aid of the data-transfer controller (DTC). This application note is a summary for quick
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SH7280
SH7285
REJ06B0809-0100/Rev
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C082
Abstract: Mark A018 SH7137
Text: APPLICATION NOTE SH7137 Group Using the DTC in the Asynchronous-Mode Transfer of Serial Data by the SCI Introduction This application note describes the transfer of serial data in asynchronous mode by the serial communications interface SCI with the aid of the data-transfer controller (DTC). This application note is a summary for quick reference of
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SH7137
SH7137
REJ06B0766-0100/Rev
C082
Mark A018
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h498
Abstract: 20203 elcon SERIES 1000 crb 455 FF0005 PMR63 ELSR32 R4F20203 H4c9 H456
Text: APPLICATION NOTE H8S/20103, H8S/20203, and H8S/20223 Groups Using a Compare-Match Signal from Timer RD to Activate the DTC Introduction The event link controller ELC in products of the H8S/20103, H8S/20203, and H8S/20223 Groups is used to set up activation of the data transfer controller (DTC) by the compare match signal for a match between the counter of timer
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H8S/20103,
H8S/20203,
H8S/20223
H8S/20103
R4F20103)
H8S/20203
R4F20203)
h498
20203
elcon SERIES 1000
crb 455
FF0005
PMR63
ELSR32
R4F20203
H4c9
H456
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DTC DATA TECHNOLOGY
Abstract: No abstract text available
Text: APPLICATION NOTE H8S Family Data Transfer Started up by Software Introduction Starts up DTC at detection of a falling edge of a port to transfer one 128-byte block. Target Device H8S/2339 Contents 1. Specifications . 2
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128-byte
H8S/2339
REJ06B0464-0100/Rev
DTC DATA TECHNOLOGY
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Untitled
Abstract: No abstract text available
Text: APPLICATION NOTE H8S/2200 Series Data Transfer Started up by Software Introduction Starts up DTC at detection of a falling edge of a port to transfer one 128-byte block. Target Device H8S/2239 Contents 1. Specifications . 2
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H8S/2200
128-byte
H8S/2239
REJ06B0317-0100Z/Rev
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FFB000
Abstract: mds101
Text: APPLICATION NOTE H8SX Family Transfer of Longword Data to Odd Addresses—DTC Edition Introduction Data in memory are accessible to an H8SX CPU as words or longwords. Data thus accessed can be allocated to any address, regardless of whether it is odd or even. The DTC is capable of operating in the same way.
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H8SX/1653F
REJ06B0651-0100/Rev
FFB000
mds101
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