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    FI1028 Search Results

    FI1028 Datasheets (2)

    Part ECAD Model Manufacturer Description Curated Datasheet Type PDF
    FI1028M Fairchild Semiconductor 3.3V LVDS Dual High Speed Differential Receiver Original PDF
    FI1028MX Fairchild Semiconductor 3.3V LVDS Dual High Speed Differential Receiver Original PDF

    FI1028 Datasheets Context Search

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    M08A

    Abstract: FI1028M
    Text: Preliminary Revised December 2000 FI1028 3.3V LVDS Dual High Speed Differential Receiver Preliminary General Description Features This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels.


    Original     		PDF FI1028 400Mbs FI1028 FI1027, M08A FI1028M

    FI1027M

    Abstract: M08A
    Text: Preliminary Revised December 2000 FI1027 3.3V LVDS Dual High Speed Differential Driver Preliminary General Description Features This dual driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350 mV which


    Original     		PDF FI1027 600Mbs FI1027 FI1028, TIA/EIA-644 FI1027M M08A

    Untitled

    Abstract: No abstract text available
    Text: FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Receiver Features Description ̇ ̇ ̇ ̇ ̇ ̇ ̇ Greater than 400Mbs Data Rate This dual receiver is designed for high-speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS


    Original     		PDF FIN1028 400Mbs 100mV, TIA/EIA-644

    SOIC127P600X175-8M

    Abstract: M08AREV13 FIN1027 FIN1028 FIN1028M FIN1028MX JESD22-A114 JESD22-A115 SOIC127P600X175 Fairchild DUAL receiver
    Text: FIN1028 — 3.3V LVDS 2-Bit High-Speed Differential Receiver Features Description ƒ ƒ ƒ ƒ ƒ ƒ ƒ Greater than 400Mbs Data Rate This dual receiver is designed for high-speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS


    Original     		PDF FIN1028 100mV, 400Mbs FIN1028 SOIC127P600X175-8M M08AREV13 FIN1027 FIN1028M FIN1028MX JESD22-A114 JESD22-A115 SOIC127P600X175 Fairchild DUAL receiver